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    Semiconductor memory device
    1.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US6049494A

    公开(公告)日：2000-04-11

    申请号：US18315

    申请日：1998-02-03

    申请人： Koji Sakui ,  Yasuo Itoh ,  Yoshihisa Iwata

    发明人： Koji Sakui ,  Yasuo Itoh ,  Yoshihisa Iwata

    IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

    CPC分类号： G11C16/10 ,  G11C16/0483

    摘要： A semiconductor memory device includes a memory cell array in which memory cell units are arranged in a matrix, each memory cell unit being constructed by connecting plural memory cells, each of which is electrically rewritable, a select gate connected to a select gate line for connecting a memory cell unit to a bitline, a precharge circuit connected to a first node of the bitline, for supplying a precharge voltage higher than an power supply voltage in programming of data, and a latch circuit connected to a second node of the bitline via a transfer gate for holding data to be programmed into a memory cell, wherein channels of the plurality of the memory cells constituting a selected memory cell unit are charged to the precharge voltage in programming of data.

    摘要翻译： 半导体存储器件包括：存储单元阵列，其中存储单元单元以矩阵形式布置;每个存储单元单元通过连接多个存储单元构成，每个存储单元可电可重写，连接到选择栅极线用于连接的选择栅极 连接到位线的第一节点的预充电电路，用于在数据编程中提供高于电源电压的预充电电压;以及锁存电路，其经由一位线连接到该位线的第二节点 用于将要编程的数据保存到存储单元中的传输门，其中构成选择的存储单元单元的多个存储单元的通道在数据编程中被充电到预充电电压。

    Non-volatile semiconductor memory device
    2.
    发明授权
    Non-volatile semiconductor memory device 失效

    公开(公告)号：US6011287A

    公开(公告)日：2000-01-04

    申请号：US31681

    申请日：1998-02-27

    申请人： Yasuo Itoh ,  Koji Sakui

    发明人： Yasuo Itoh ,  Koji Sakui

    IPC分类号： G11C16/04 ,  H01L27/115 ,  H01L29/72

    CPC分类号： H01L27/115 ,  G11C16/0483

    摘要： In a NAND EEPROM using the local self-boosting system, an intermediate voltage which allows a memory cell adjacent to a selected memory cell to be turned on is applied to the control gate of the adjacent memory cell. As a result, even if the adjacent memory cell is in a normally-off state, the potential of a bit line can be transmitted to the adjacent memory cell. Thus, the reliability of the write inhibition in a non-selected NAND memory cell column is improved, while data can be written at random into a plurality of memory cells in a selected NAND memory cell column. When data is to be erased, an absolute value of an erasing voltage applied to a control gate can be less. As a result, data can be erased by a lower erasure voltage than that required in the conventional art. Consequently, the element refinement, the reliability and the yield can be further improved.

    Non-volatile semiconductor memory device
    3.
    发明授权
    Non-volatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US6107658A

    公开(公告)日：2000-08-22

    申请号：US468928

    申请日：1999-12-22

    申请人： Yasuo Itoh ,  Koji Sakui

    发明人： Yasuo Itoh ,  Koji Sakui

    IPC分类号： G11C16/04 ,  H01L27/115 ,  H01L29/72

    CPC分类号： H01L27/115 ,  G11C16/0483

    摘要： In a NAND EEPROM using the local self-boosting system, an intermediate voltage which allows a memory cell adjacent to a selected memory cell to be turned on is applied to the control gate of the adjacent memory cell. As a result, even if the adjacent memory cell is in a normally-off state, the potential of a bit line can be transmitted to the adjacent memory cell. Thus, the reliability of the write inhibition in a non-selected NAND memory cell column is improved, while data can be written at random into a plurality of memory cells in a selected NAND memory cell column. When data is to be erased, an absolute value of an erasing voltage applied to a control gate can be less. As a result, data can be erased by a lower erasure voltage than that required in the conventional art. Consequently, the element refinement, the reliability and the yield can be further improved.

    摘要翻译： 在使用本地自增强系统的NAND EEPROM中，将允许与所选存储单元相邻的存储单元导通的中间电压被施加到相邻存储单元的控制栅极。 因此，即使相邻的存储单元处于常关状态，也可以将位线的电位发送到相邻的存储单元。 因此，提高了在非选择的NAND存储单元列中写入禁止的可靠性，同时可以将数据随机写入到所选NAND存储单元列中的多个存储单元中。 当要擦除数据时，施加到控制栅极的擦除电压的绝对值可以较小。 结果，可以通过比传统技术中所需的更低的擦除电压来擦除数据。 因此，可以进一步提高元素精化，可靠性和产率。

    Non-volatile semiconductor memory device for storing multivalue data and readout/write-in method therefor
    7.
    发明授权
    Non-volatile semiconductor memory device for storing multivalue data and readout/write-in method therefor 失效
    用于存储多值数据和其读出/写入方法的非易失性半导体存储器件

    公开(公告)号：US5751634A

    公开(公告)日：1998-05-12

    申请号：US647629

    申请日：1996-05-15

    申请人： Yasuo Itoh

    发明人： Yasuo Itoh

    IPC分类号： G11C17/00 ,  G11C11/56 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C7/00

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/26 ,  G11C2211/5642 ,  G11C2211/5647

    摘要： Memory cells each for storing 2-bit data are connected to a bit line. First and second flip-flop circuits are coupled to the bit line. The first flip-flop circuit holds the lower bit of 2-bit data read out from or written into the memory cell and the second flip-flop circuit holds the upper bit of 2-bit data read out from or written into the memory cell. At the data readout time, the upper bit is first read out from the memory cell and then the lower bit is read out from the memory cell. At the data writing time, the upper bit is first written into the memory cell and then the lower bit is written into the memory cell.

    摘要翻译： 每个用于存储2位数据的存储单元连接到位线。 第一和第二触发器电路耦合到位线。 第一触发器电路保持从存储单元读出或写入存储单元的2位数据的低位，并且第二触发器电路保持从存储单元读出或写入存储单元的2位数据的高位。 在数据读出时，首先从存储单元读出高位，然后从存储单元读出低位。 在数据写入时，首先将高位写入存储单元，然后将较低位写入存储单元。

    Non-volatile semiconductor memory device with verify mode for verifying data written to memory cells
    8.
    发明授权
    Non-volatile semiconductor memory device with verify mode for verifying data written to memory cells 失效
    具有用于验证写入存储单元的数据的验证模式的非易失性半导体存储器件

    公开(公告)号：US5557568A

    公开(公告)日：1996-09-17

    申请号：US427265

    申请日：1995-04-24

    申请人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

    发明人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

    IPC分类号： G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

    CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/3454 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1048

    摘要： A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element, and a transistor charges the bit line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range. A data setting circuit for connects one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.

    摘要翻译： 非挥发性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路。 位线通过开关元件连接到触发器电路，晶体管对位线进行充电。 连接到位线并具有MOS晶体管结构的非易失性存储单元将其阈值设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，存储单元的阈值 在触发器电路保持在第一状态的同时触发器电路保持在第二状态，并且当触发器电路保持在第二状态时阈值的偏移不被影响时，从第一阈值范围向第二阈值范围移位， 在写模式之后，当阈值保持在第二阈值范围内时，位线被充电晶体管保持在电荷电位。 一种数据设定电路，用于在触发电路的第一和第二信号节点之一连接到预定电位，当位线在验证模式下处于充电电位时，从而将触发器电路设置在第二状态，而与 在验证模式之前的状态。