Abstract:
A catheter product package and method of forming same in which the package comprises a sheet material wrapped about the catheter product to form a package for the catheter product. The catheter product extends generally longitudinally within the package, and the sheet material extends from a point beyond the proximal end to a point beyond the distal end of the catheter product. The sheet material of the package is wrapped about the catheter product in a manner defining confronting proximal end edges, confronting distal end edges, and confronting side edges. The confronting proximal end edges, distal end edges and side edges of the sheet material are joined by a seal after the sheet material is wrapped about the catheter product to define a sealed cavity. The sheet material has a tear strip affixed to it which causes the sheet material to tear along the tear strip to thereby cause the package to open along an intended opening line. A method of forming a package for a catheter product comprises the steps of providing a sheet material for the package and placing the catheter product on the sheet material. It also includes affixing a tear strip to the sheet material and wrapping the sheet material around the catheter product. Further, the method includes the step of sealing the sheet material to form a sealed cavity with the catheter product being disposed within the sealed cavity.
Abstract:
A composition for a low lead ingot comprising primarily copper and including tin, zinc, sulfur, phosphorus, nickel. The composition may contain carbon. The low lead ingot, when solidified, includes sulfur or sulfur containing compounds such as sulfides distributed through the ingot. The presence and a substantially uniform distribution of these sulfur compounds imparts improved machinability and better mechanical properties.
Abstract:
A composition for a low lead ingot comprising primarily copper and including tin, zinc, sulfur, phosphorus, nickel. The composition may contain manganese. The low lead ingot, when solidified, includes sulfur or sulfur containing compounds such as sulfides distributed through the ingot. The presence and a substantially uniform distribution of these sulfur compounds imparts improved machinability and better mechanical properties.
Abstract:
Various embodiments comprise apparatus, methods, and systems including method comprising searching for a group address among a plurality of group addresses in a mapping table, and if a match is found, performing a memory operation on a first plurality of memory blocks indicated by the mapping table, and if a match is not found, performing a memory operation on a second plurality of memory blocks, the second plurality of memory blocks having the group address.
Abstract:
Methods and apparatus may operate to receive allocation requests from a processor configured to manage memory comprising a non-volatile memory device configurable as a plurality of blocks comprising a plurality of sectors, assign partial page blocks from the plurality of blocks for memory storage, fill some of the sectors by storing data bits associated with the allocation request in the at least one of the plurality of sectors, determine that the sectors are full, assigning a full page block from the plurality of blocks, and transfer the data bits associated with the allocation request from the partial page blocks to the full page block. Other apparatus, systems, and methods are disclosed.
Abstract:
A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.
Abstract:
Handling electronic coupons includes accessing information indicating association of an electronic coupon with an account of a user that identifies multiple retail entities associated with the user. Information indicating association of electronic coupons with the user's account may be transmitted to respective computer systems associated with the multiple retail entities. The computer systems may associate electronic coupons with the user such that the user may redeem the electronic coupons at a retail store upon presentation of a user identifier. When the user redeems an electronic coupon, cancellation information for the electronic coupon may be transmitted to the computer systems of other retail entities associated with the user. Receipt of the cancellation information may cause the respective computer systems to cancel the redeemability of the electronic coupon such that the user is prevented from redeeming the electronic coupon at a retail store associated with the corresponding retail entity.
Abstract:
A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.
Abstract:
A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an input data strobe, the last two bits are transmitted over the bus, which eliminates the need for the precise counting of input data strobe pulses. The data bus circuit is compatible with both DDR1 and DDR2 operating modes.
Abstract:
A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an input data strobe, the last two bits are transmitted over the bus, which eliminates the need for the precise counting of input data strobe pulses. The data bus circuit is compatible with both DDR1 and DDR2 operating modes.