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    Semiconductor device having laterally offset stacked semiconductor dies
    73.
    发明授权
    Semiconductor device having laterally offset stacked semiconductor dies 有权

    公开(公告)号：US11037910B2

    公开(公告)日：2021-06-15

    申请号：US16933649

    申请日：2020-07-20

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  Ashok Pachamuthu

    IPC: H01L25/065 ,  H01L25/00

    Abstract: Semiconductor devices including stacked semiconductor dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die coupled to a package substrate and a second semiconductor die stacked over the first semiconductor die and laterally offset from the first semiconductor die. The second semiconductor die can accordingly include an overhang portion that extends beyond a side of the first semiconductor die and faces the package substrate. In some embodiments, the second semiconductor die includes bond pads at the overhang portion that are electrically coupled to the package substrate via conductive features disposed therebetween. In certain embodiments, the first semiconductor die can include second bond pads electrically coupled to the package substrate via wire bonds.

    MEMORY MODULES AND MEMORY PACKAGES INCLUDING GRAPHENE LAYERS FOR THERMAL MANAGEMENT
    75.
    发明申请
    MEMORY MODULES AND MEMORY PACKAGES INCLUDING GRAPHENE LAYERS FOR THERMAL MANAGEMENT 有权

    公开(公告)号：US20210036125A1

    公开(公告)日：2021-02-04

    申请号：US16530757

    申请日：2019-08-02

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  George E. Pax ,  Yogesh Sharma ,  Gregory A. King ,  Thomas H. Kinsley ,  Randon K. Richards

    IPC: H01L29/66 ,  H05K1/11 ,  H01L23/495

    Abstract: Systems, apparatuses, and methods relating to memory devices and packaging are described. A device, such as a dual inline memory module (DIMM) or other electronic device package, may include a substrate with a layer of graphene configured to conduct thermal energy (e.g., heat) away from components mounted or affixed to the substrate. In some examples, a DIMM includes an uppermost or top layer of graphene that is exposed to the air and configured to allow connection of memory devices (e.g., DRAMs) to be soldered to the conducting pads of the substrate. The graphene may be in contact with parts of the memory device other than the electrical connections with the conducting pads and may thus be configured as a heat sink for the device. Other thin, conductive layers of may be used in addition to or as an alternative to graphene. Graphene may be complementary to other heat sink mechanisms.

    SEMICONDUCTOR DEVICE HAVING LATERALLY OFFSET STACKED SEMICONDUCTOR DIES
    77.
    发明申请
    SEMICONDUCTOR DEVICE HAVING LATERALLY OFFSET STACKED SEMICONDUCTOR DIES 审中-公开

    公开(公告)号：US20200350293A1

    公开(公告)日：2020-11-05

    申请号：US16933649

    申请日：2020-07-20

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  Ashok Pachamuthu

    IPC: H01L25/065 ,  H01L25/00

    Abstract: Semiconductor devices including stacked semiconductor dies and associated systems and methods are disclosed herein. In one embodiment, a semiconductor device includes a first semiconductor die coupled to a package substrate and a second semiconductor die stacked over the first semiconductor die and laterally offset from the first semiconductor die. The second semiconductor die can accordingly include an overhang portion that extends beyond a side of the first semiconductor die and faces the package substrate. In some embodiments, the second semiconductor die includes bond pads at the overhang portion that are electrically coupled to the package substrate via conductive features disposed therebetween. In certain embodiments, the first semiconductor die can include second bond pads electrically coupled to the package substrate via wire bonds.

    Graphics processing unit and high bandwidth memory integration using integrated interface and silicon interposer
    78.
    发明授权
    Graphics processing unit and high bandwidth memory integration using integrated interface and silicon interposer 有权

    公开(公告)号：US10770398B2

    公开(公告)日：2020-09-08

    申请号：US16180538

    申请日：2018-11-05

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  Owen R. Fay

    IPC: H01L23/538 ,  H01L27/108 ,  H01L27/092 ,  H01L25/18

    Abstract: A semiconductor device assembly that includes a second side of an interposer being connected to a first side of a substrate. A plurality of interconnects may be connected to a second side of the substrate. First and second semiconductor devices are connected directly to the first side of the interposer. The interposer is configured to enable the first semiconductor device and the second semiconductor device to communicate with each other through the interposer. The interposer may be a silicon interposer that includes complementary metal-oxide-semiconductor circuits. The first semiconductor device may be a processing unit and the second semiconductor device may be a memory device, which may be a high bandwidth memory device. A method of making a semiconductor device assembly includes attaching both a memory device and a processing unit directly to a first side of an interposer and connecting a second side of the interposer to a substrate.

    Semiconductor device with flexible circuit for enabling non-destructive attaching and detaching of device to system board
    80.
    发明授权
    Semiconductor device with flexible circuit for enabling non-destructive attaching and detaching of device to system board 有权

    公开(公告)号：US10276487B1

    公开(公告)日：2019-04-30

    申请号：US15787471

    申请日：2017-10-18

    Applicant: Micron Technology, Inc.

    Inventor： Chan H. Yoo ,  Eiichi Nakano

    IPC: H01L23/498 ,  H01R12/77 ,  H01L23/538 ,  H01L41/047 ,  H01L23/00 ,  H01L21/56 ,  H01R12/71 ,  H01R12/70

    Abstract: A semiconductor device assembly that includes a flexible member having a first portion connected to a substrate and a connector attached to a second portion of the flexible member. The connector is electrically connected to the substrate via a conducting layer within the flexible member. The substrate may be a semiconductor device, such as a chip. The connector may be configured to connect the semiconductor device to another semiconductor device assembly or a system board, such as a printed circuit board. A material may encapsulate at least a portion of the substrate of the semiconductor assembly. The semiconductor device assembly may be formed by selectively connecting the flexible member to a first substrate. A second substrate and connector may then be connected to the flexible member. A release layer may be used to release the assembly of the second substrate, flexible member, and connector from the first substrate.

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