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公开(公告)号：US20170177019A1
公开(公告)日：2017-06-22
申请号：US15117681
申请日：2016-06-06
Applicant: Micron Technology, Inc.
IPC: G05F3/26
CPC classification number: G05F3/26
Abstract: A reference voltage generator is disclosed that may provide a plurality of reference voltages. A reference voltage generator may include a voltage divider, a multiplexer coupled to the voltage divider, an operational amplifier that may receive a voltage from the multiplexer, and a plurality of resistors that may receive an output from the operational amplifier. The reference voltages may be provided from output terminals coupled to the resistors. A reference voltage generator may include a voltage divider, two multiplexers coupled to the voltage divider, an operational amplifier coupled to each multiplexer, and a plurality of resistors coupled between the outputs of the two operational amplifiers. Reference voltages may be provided from output terminals coupled to the resistors.
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公开(公告)号：US20140334241A1
公开(公告)日：2014-11-13
申请号：US14444762
申请日：2014-07-28
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Ming H. Li , Dong Pan
CPC classification number: G11C8/18 , G05F5/00 , G11C8/08 , G11C8/10 , H03K3/0315 , H03K2005/00032 , H03L1/00
Abstract: Circuits, apparatuses, and methods are disclosed for oscillators. In one such example oscillator circuit, a plurality of delay stages are coupled in series. A variable delay circuit stage is coupled to the plurality of delay stages and is configured to delay a signal through the variable delay circuit stage by a variable delay. The variable delay increases responsive to a rising magnitude of a supply voltage provided to the variable delay circuit stage.
Abstract translation: 公开了用于振荡器的电路，装置和方法。 在一个这样的示例性振荡器电路中，多个延迟级串联耦合。 可变延迟电路级耦合到多个延迟级，并且被配置为将可变延迟电路级的信号延迟可变延迟。 响应于提供给可变延迟电路级的电源电压的上升幅度，可变延迟增加。
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公开(公告)号：US20240347100A1
公开(公告)日：2024-10-17
申请号：US18629445
申请日：2024-04-08
Applicant: Micron Technology, Inc.
Inventor： Yuan He , Yang Lu , Dong Pan , Kang-Yong Kim
IPC: G11C11/4076 , G11C11/406 , G11C11/408
CPC classification number: G11C11/4076 , G11C11/40622 , G11C11/4085
Abstract: A value associated with a number of accesses of a word line and a length of said accesses may be stored on said word line. A timer may provide a periodic signal that increments a counter to update the value. The updated value may then be written back to the word line. In some examples, a memory device including the word lines may have a specification that prevents the word line from closing prior to writing the updated value to the word line.
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公开(公告)号：US11984184B2
公开(公告)日：2024-05-14
申请号：US17873869
申请日：2022-07-26
Applicant: Micron Technology, Inc.
Inventor： Subhasis Sasmal , Dong Pan
IPC: G11C29/50 , G01R19/165 , G11C29/12
CPC classification number: G11C29/50004 , G01R19/16528 , G01R19/16533 , G11C29/12005 , G11C2029/5004
Abstract: An electronic device, such as a memory device, may include various circuit components. The electronic device may also include one or more voltage testing circuits to determine whether signals of one or more of the circuit components are within acceptable voltage ranges of the respective circuit components. Systems and methods are described to improve correct voltage measurement of the received signals by a voltage testing circuit. In particular, multiple supply voltage levels are provided to different components of the voltage testing circuit to provide a sufficient headroom voltage gap between received signals and the supply voltages. For example, some active circuits (e.g., operational amplifiers) of the voltage testing circuit may receive a higher supply voltage of the electronic device compared to one or more other circuits of the voltage testing circuit.
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公开(公告)号：US11967355B2
公开(公告)日：2024-04-23
申请号：US17844207
申请日：2022-06-20
Applicant: Micron Technology, Inc.
Inventor： Wei Lu Chu , Dong Pan
IPC: G11C11/4074 , G11C11/4076
CPC classification number: G11C11/4074 , G11C11/4076
Abstract: A device includes source circuitry comprising a first portion of a current mirror and a first transistor. The device also includes load circuitry comprising a second portion of the current mirror and a second transistor, wherein the load circuitry is disposed at a distance from the source circuitry. The device further includes a path coupled to a first gate of the first transistor and to a second gate of the second transistor, wherein the path provides a predetermined voltage to both of the first gate of the first transistor and to the second gate of the second transistor.
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Patent Agency Ranking
公开(公告)号：US11829177B2
公开(公告)日：2023-11-28
申请号：US17391655
申请日：2021-08-02
Applicant: Micron Technology, Inc.
Inventor： Suresh Chattu , Wei Lu Chu , Dong Pan
IPC: G11C11/4074 , G05F3/26 , G05F1/575
CPC classification number: G05F3/262 , G05F1/575 , G11C11/4074
Abstract: A semiconductor device may include a bandgap circuit that outputs a reference voltage. The bandgap circuit may include a bandgap core circuit and a startup circuit coupled to the bandgap core circuit. The startup circuit may connect a voltage source to a node that corresponds to an output of the bandgap core circuit in response to the bandgap core circuit being initialized. The startup circuit may also disconnect the voltage source from the node in response to the output voltage being equal to or greater than a desired voltage (e.g., a threshold voltage) and one or more local voltages of the bandgap core circuit being equal to or greater than a local threshold voltage.
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公开(公告)号：US20230253928A1
公开(公告)日：2023-08-10
申请号：US17583018
申请日：2022-01-24
Applicant: Micron Technology, Inc.
Inventor： Wei Lu Chu , Dong Pan
IPC: H03F1/30 , H03F3/21 , H03F1/02 , H02M3/155 , G11C11/4074
CPC classification number: H03F1/301 , G11C11/4074 , H02M3/155 , H03F1/0233 , H03F3/211 , H03F2200/504
Abstract: Systems and devices are provided for tracking bandgap current generated by a bandgap circuit and mitigation of leakage current regardless of variations in PVT conditions. An apparatus may include one or more power amplifiers that powers components of the apparatus and comprising a transistor. The apparatus may also include bandgap current mirroring circuitry that generates a mirrored current that mirrors a received current that is process, voltage, and temperature (PVT) independent. The apparatus may also include a bulk voltage generator circuit including an amplifier having an input coupled to the bandgap current mirroring circuitry. Bulk voltage control circuitry is coupled to an output of the amplifier and generates a bulk voltage based on the relationship between the mirrored current and the leakage current.
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公开(公告)号：US11632084B2
公开(公告)日：2023-04-18
申请号：US17127172
申请日：2020-12-18
Applicant: Micron Technology, Inc.
Inventor： Wei Lu Chu , Zhi Qi Huang , Dong Pan
Abstract: Methods, systems, and devices for operating an amplifier with a controllable pull-down capability are described. A memory device may include a memory array and a power circuit that generates an internal signal for components in the memory array. The power circuit may include an amplifier and a power transistor that is coupled with the amplifier. A pull-down capability of the amplifier may be controllable using an external signal that is based on a difference between a reference signal and the internal signal. The power circuit may also include a comparator that is coupled with the amplifier and configured to compare the reference signal and the internal signal. Components of the comparator may be integrated with components of the amplifier, may share a bias circuit, and may use nodes within the amplifier to control the comparator. A signal output by the comparator may control the pull-down capability of the amplifier.
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79.发明授权公开(公告)号：US11626152B2
公开(公告)日：2023-04-11
申请号：US17324621
申请日：2021-05-19
Applicant: MICRON TECHNOLOGY, INC.
IPC: G11C16/08 , G11C7/00 , G11C11/406
Abstract: Apparatuses and methods for pure-time, self-adopt sampling for RHR refresh. An example apparatus includes a memory bank comprising a plurality of rows each associated with a respective row address, and a sampling timing generator circuit configured to provide a timing signal having a plurality of pulses. Each of the plurality of pulses is configured to initiate sampling of a respective row address associated with a row of the plurality of rows to detect a row hammer attack. The sampling timing generator includes first circuitry configured to provide a first subset of pulses of the plurality of pulses during a first time period and includes second circuitry configured to initiate provision of a second subset of pulses of the plurality of pulses during a second time period after the first time period.
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公开(公告)号：US11587602B2
公开(公告)日：2023-02-21
申请号：US17526846
申请日：2021-11-15
Applicant: Micron Technology, Inc.
Inventor： Zhi Qi Huang , Wei Lu Chu , Dong Pan
Abstract: Methods, systems, and devices for timing signal delay compensation in a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous relative to an input signal. To support asynchronous timing, a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. In accordance with examples as disclosed herein, a memory device may include delay components having a variable and configurable impedance, where the configurable impedance may be based at least in part on a configuration signal generated at the memory device. A configuration signal may be generated based on fabrication characteristics of the memory device, or based on operating conditions of the memory device, or various combinations thereof.
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