公开(公告)号：US11928590B2

公开(公告)日：2024-03-12

申请号：US17161210

申请日：2021-01-28

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes

IPC: G06N3/08 ,  G06F1/3206 ,  G06F1/3287 ,  G06V10/94

CPC classification number: G06N3/08 ,  G06F1/3206 ,  G06F1/3287 ,  G06V10/94 ,  G06V10/955 ,  Y02D10/00

Abstract: A device includes a state machine. The state machine includes a plurality of blocks, where each of the blocks includes a plurality of rows. Each of these rows includes a plurality of programmable elements. Furthermore, each of the programmable elements are configured to analyze at least a portion of a data stream and to selectively output a result of the analysis. Each of the plurality of blocks also has corresponding block activation logic configured to dynamically power-up the block.

公开(公告)号：US11836081B2

公开(公告)日：2023-12-05

申请号：US17155433

申请日：2021-01-22

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes ,  Inderjit Singh Bains

IPC: G06F12/08 ,  G06F12/0875 ,  G06F9/448 ,  G06N3/02 ,  G06F3/06 ,  G06F3/02

CPC classification number: G06F12/0875 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0683 ,  G06F9/4498 ,  G06N3/02 ,  G06F2212/60

Abstract: A data analysis system to analyze data. The data analysis system includes a data buffer configured to receive data to be analyzed. The data analysis system also includes a state machine lattice. The state machine lattice includes multiple data analysis elements and each data analysis element includes multiple memory cells configured to analyze at least a portion of the data and to output a result of the analysis. The data analysis system includes a buffer interface configured to receive the data from the data buffer and to provide the data to the state machine lattice.

公开(公告)号：US11830243B2

公开(公告)日：2023-11-28

申请号：US17154671

申请日：2021-01-21

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  Steven P. King

IPC: G06V10/94 ,  G06F16/9032 ,  G06F13/40

CPC classification number: G06V10/955 ,  G06F16/90332 ,  G06F13/4027

Abstract: Disclosed are methods and devices, among which is a device including a bus translator. In some embodiments, the device also includes a core module and a core bus coupled to the core module. The bus translator may be coupled to the core module via the core bus, and the bus translator may be configured to translate between signals from a selected one of a plurality of different types of buses and signals on the core bus.

公开(公告)号：US11782859B2

公开(公告)日：2023-10-10

申请号：US17184372

申请日：2021-02-24

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  Steven P. King

IPC: G06F13/28 ,  G06F13/38 ,  G06F13/40

CPC classification number: G06F13/28 ,  G06F13/38 ,  G06F13/385 ,  G06F13/4004 ,  G06F13/4027

Abstract: Disclosed are devices and methods, among which is a device peripheral to a controller device that is used to provide memory access to the controller device. In some embodiments, the device may determine and provide a response of the device to requests from the separate device.

公开(公告)号：US11580055B2

公开(公告)日：2023-02-14

申请号：US17007636

申请日：2020-08-31

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown ,  Paul Glendenning ,  Paul D. Dlugosch

IPC: G06F15/78 ,  G06N20/00 ,  G06F9/448 ,  G06F1/3225 ,  G06F13/42 ,  G05B19/045 ,  G06F3/06

Abstract: A device includes a plurality of blocks. Each block of the plurality of blocks includes a plurality of rows. Each row of the plurality of rows includes a plurality of configurable elements and a routing line, whereby each configurable element of the plurality of configurable elements includes a data analysis element comprising a plurality of memory cells, wherein the data analysis element is configured to analyze at least a portion of a data stream and to output a result of the analysis. Each configurable element of the plurality of configurable elements also includes a multiplexer configured to transmit the result to the routing line.

公开(公告)号：US11151140B2

公开(公告)日：2021-10-19

申请号：US16206290

申请日：2018-11-30

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  David R. Brown

IPC: G06F16/2455 ,  G06F16/903 ,  G06K9/00 ,  G06F1/3296

Abstract: Apparatuses and methods are provided for reducing power consumption in a pattern-recognition processor. A power control circuit may be coupled to a block of programmed state machines to enable selective activation and deactivation of the block during a pattern search. The block may be deactivated if the pattern search is no longer active in that block and activated when needed by the pattern search. Additionally, the block may be deactivated based on an identifier of the data stream being searched. Excess blocks not used for any programmed state machines may be disabled such that they are not refreshed during a memory cycle.

公开(公告)号：US10942877B2

公开(公告)日：2021-03-09

申请号：US16799444

申请日：2020-02-24

Applicant: Micron Technology, Inc.

Inventor： Harold B Noyes ,  Steven P. King

IPC: G06F13/38 ,  G06F13/28 ,  G06F13/40

Abstract: Disclosed are devices and methods, among which is a device peripheral to a controller device that is used to provide memory access to the controller device. In some embodiments, the device may determine and provide a response of the device to requests from the separate device.

公开(公告)号：US10817569B2

公开(公告)日：2020-10-27

申请号：US15806073

申请日：2017-11-07

Applicant: Micron Technology Inc.

Inventor： Harold B Noyes ,  David R. Brown

IPC: G06F16/903 ,  G06F11/30

Abstract: Systems and methods are disclosed for saving and restoring the search state of a pattern-recognition processor. Embodiments include a pattern-recognition processor having a state variable array and a state variable storage array stored in on-chip memory (on-silicon memory with the processor). State variable storage control logic of the pattern-recognition processor may control the saving of state variables from the state variable array to the state variable storage array. The state variable storage control logic may also control restoring of the state variables from the state variable storage array to restore a search state.

公开(公告)号：US10671295B2

公开(公告)日：2020-06-02

申请号：US16694584

申请日：2019-11-25

Applicant: Micron Technology, Inc.

Inventor： David R. Brown ,  Harold B Noyes

IPC: G06F9/312 ,  G06F3/06 ,  G06N3/02 ,  G06F8/41

Abstract: A state machine engine includes a state vector system. The state vector system includes an input buffer configured to receive state vector data from a restore buffer and to provide state vector data to a state machine lattice. The state vector system also includes an output buffer configured to receive state vector data from the state machine lattice and to provide state vector data to a save buffer.

公开(公告)号：US20200133893A1

公开(公告)日：2020-04-30

申请号：US16726523

申请日：2019-12-24

Applicant: Micron Technology, Inc.

Inventor： Debra Bell ,  Paul Glendenning ,  David R. Brown ,  Harold B Noyes

IPC: G06F13/12 ,  G06F13/40 ,  G06F13/28

Abstract: In one embodiment, a system includes a bus interface including a first processor, an indirect address storage storing a number of indirect addresses, and a direct address storage storing a number of direct addresses. The system also includes a number of devices connected to the bus interface and configured to analyze data. Each device of the number of devices includes a state machine engine. The bus interface is configured to receive a command from a second processor and to transmit an address for loading into the state machine engine of at least one device of the number of devices. The address includes a first address from the number of indirect addresses or a second address from the number of direct addresses.