公开(公告)号：US20050132365A1

公开(公告)日：2005-06-16

申请号：US10738687

申请日：2003-12-16

申请人： Rajesh Madukkarumukumana ,  Gilbert Neiger ,  Ioannis Schoinas

发明人： Rajesh Madukkarumukumana ,  Gilbert Neiger ,  Ioannis Schoinas

IPC分类号： G06F9/455 ,  G06F9/50

CPC分类号： G06F9/5077

摘要： The present disclosure relates to the resource management of virtual machine(s) using hardware address mapping, and, more specifically, to facilitate direct access to devices from virtual machines, utilizing control of hardware address translation facilities.

摘要翻译： 本公开涉及使用硬件地址映射的虚拟机的资源管理，更具体地，涉及利用硬件地址转换设施的控制来促进从虚拟机直接访问设备。

公开(公告)号：US20050125580A1

公开(公告)日：2005-06-09

申请号：US10731171

申请日：2003-12-08

申请人： Rajesh Madukkarumukumana ,  Ioannis Schoinas ,  Gilbert Neiger

发明人： Rajesh Madukkarumukumana ,  Ioannis Schoinas ,  Gilbert Neiger

IPC分类号： G06F9/455 ,  G06F9/48 ,  G06F12/00

CPC分类号： G06F9/45533 ,  G06F9/4812

摘要： The present disclosure relates to the handling of interrupts in a environment that utilizes virtual machines, and, more specifically, to the steering of interrupts between multiple logical processors running virtual machines.

摘要翻译： 本公开涉及在利用虚拟机的环境中的中断的处理，更具体地，涉及在运行虚拟机的多个逻辑处理器之间的中断的转向。

公开(公告)号：US20100011187A1

公开(公告)日：2010-01-14

申请号：US12584138

申请日：2009-09-01

申请人： Ioannis Schoinas ,  Gilbert Neiger ,  Rajesh Madukkarumukumana ,  Ku-Jei King ,  Richard Uhlig ,  Achmed Rumi Zahir ,  Koichi Yamada

发明人： Ioannis Schoinas ,  Gilbert Neiger ,  Rajesh Madukkarumukumana ,  Ku-Jei King ,  Richard Uhlig ,  Achmed Rumi Zahir ,  Koichi Yamada

IPC分类号： G06F12/10 ,  G06F12/00 ,  G06F13/28

CPC分类号： G06F12/1081 ,  G06F12/1036 ,  G06F12/109

摘要： An embodiment of the present invention is a technique to enhance address translation performance. A register stores capability indicators to indicate capability supported by a circuit in a chipset for address translation of a guest physical address to a host physical address. A plurality of multi-level page tables is used for page walking in the address translation. Each of the page tables has page table entries. Each of the page table entries has at least an entry specifier corresponding to the capability indicated by the capability indicators.

摘要翻译： 本发明的一个实施例是一种增强地址转换性能的技术。 寄存器存储用于指示由芯片组中的电路支持的能力指示符，用于将客体物理地址地址转换为主机物理地址。 在地址转换中使用多个多级页表进行页面行走。 每个页表都有页表项。 每个页表条目至少具有与能力指示符指示的能力对应的条目说明符。

公开(公告)号：US07334107B2

公开(公告)日：2008-02-19

申请号：US10956206

申请日：2004-09-30

申请人： Ioannis Schoinas ,  Rajesh Madukkarumukumana ,  Gilbert Neiger ,  Richard Uhlig ,  Balaji Vembu

发明人： Ioannis Schoinas ,  Rajesh Madukkarumukumana ,  Gilbert Neiger ,  Richard Uhlig ,  Balaji Vembu

IPC分类号： G06F12/00 ,  G06F13/28

CPC分类号： G06F12/1027 ,  G06F12/1081 ,  G06F2212/151 ,  G06F2212/683

摘要： An embodiment of the present invention is a technique to provide cache support for direct memory access address translation. A cache structure stores cached entries used in address translation of a guest physical address to a host physical address. The guest physical address corresponds to a guest domain identified by a guest domain identifier in an input/output (I/O) transaction requested by an I/O device. A register stores an invalidating domain identifier identifying an invalidating domain and an indicator indicating invalidating an entry in the cached entries having a tag.

摘要翻译： 本发明的实施例是提供用于直接存储器访问地址转换的高速缓存支持的技术。 高速缓存结构将客户物理地址的地址转换中使用的缓存条目存储到主机物理地址。 访客物理地址对应于由I / O设备请求的输入/输出（I / O）事务中的来宾域标识符标识的访客域。 寄存器存储标识无效域的无效域标识符和指示使具有标签的缓存条目中的条目无效的指示符。

公开(公告)号：US20060288130A1

公开(公告)日：2006-12-21

申请号：US11157675

申请日：2005-06-21

申请人： Rajesh Madukkarumukumana ,  Udo Steinberg ,  Steven Bennett ,  Andrew Anderson ,  Gilbert Neiger

发明人： Rajesh Madukkarumukumana ,  Udo Steinberg ,  Steven Bennett ,  Andrew Anderson ,  Gilbert Neiger

IPC分类号： G06F13/28

CPC分类号： G06F12/1081 ,  G06F13/28

摘要： A apparatus is disclosed. The apparatus includes a remapping circuit to facilitate access of one or more I/O devices to a memory device for direct memory access (DMA) transactions. The remapping circuit includes a translation mechanism to perform memory address translations for I/O DMA transactions via address window-based translations.

摘要翻译： 公开了一种装置。 该装置包括重新映射电路，以便于将一个或多个I / O设备访问到用于直接存储器访问（DMA）事务的存储器设备。 重新映射电路包括一个翻译机制，用于通过地址窗口的翻译来执行用于I / O DMA事务的存储器地址转换。

公开(公告)号：US20060130060A1

公开(公告)日：2006-06-15

申请号：US11008911

申请日：2004-12-10

申请人： Andrew Anderson ,  Steven Bennett ,  Erik Cota-Robles ,  Alain Kagi ,  Gilbert Neiger ,  Rajesh Madukkarumukumana ,  Sebastian Schoenberg ,  Richard Uhlig ,  Michael Rothman ,  Vincent Zimmer ,  Stalinselvaraj Jeyasingh

发明人： Andrew Anderson ,  Steven Bennett ,  Erik Cota-Robles ,  Alain Kagi ,  Gilbert Neiger ,  Rajesh Madukkarumukumana ,  Sebastian Schoenberg ,  Richard Uhlig ,  Michael Rothman ,  Vincent Zimmer ,  Stalinselvaraj Jeyasingh

IPC分类号： G06F9/455

CPC分类号： G06F9/45533

摘要： In some embodiments, the invention involves a system to deprivilege components of a virtual machine monitor and enable deprivileged service virtual machines (SVMs) to handle selected trapped events. An embodiment of the invention is a hybrid VMM operating on a platform with hardware virtualization support. The hybrid VMM utilizes features from both hypervisor-based and host-based VMM architectures. In at least one embodiment, the functionality of a traditional VMM is partitioned into a small platform-dependent part called a micro-hypervisor (MH) and one or more platform-independent parts called service virtual machines (SVMs). The micro-hypervisor operates at a higher virtual machine (VM) privilege level than any SVM, while the SVM and other VMs may still have access to any instruction set architecture (ISA) privilege level. Other embodiments are described and claimed.

摘要翻译： 在一些实施例中，本发明涉及一种剥夺虚拟机监视器组件的系统，并使得被剥夺虚拟机的虚拟机（SVM）能够处理选定的被捕获的事件。 本发明的实施例是在具有硬件虚拟化支持的平台上运行的混合VMM。 混合VMM利用基于虚拟机管理程序和基于主机的VMM架构的功能。 在至少一个实施例中，传统VMM的功能被划分为称为微管理程序（MH）的小平台相关部分和称为服务虚拟机（SVM）的一个或多个平台无关部件。 微型管理程序在比任何SVM更高的虚拟机（VM）权限级别运行，而SVM和其他VM可能仍然可以访问任何指令集体系结构（ISA）特权级别。 描述和要求保护其他实施例。

公开(公告)号：US07127548B2

公开(公告)日：2006-10-24

申请号：US10124641

申请日：2002-04-16

申请人： Steve Bennett ,  Andrew V. Anderson ,  Erik Cota-Robles ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Gilbert Neiger ,  Richard Uhlig ,  Michael A. Kozuch

发明人： Steve Bennett ,  Andrew V. Anderson ,  Erik Cota-Robles ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Gilbert Neiger ,  Richard Uhlig ,  Michael A. Kozuch

IPC分类号： G06F12/00

CPC分类号： G06F9/45533 ,  G06F9/468

摘要： In one embodiment, a command pertaining to one or more portions of a register is received from guest software. Further, a determination is made as to whether the guest software has access to all of the requested portions of the register based on indicators within a mask field that correspond to the requested portions of the register. If the guest software has access to all of the requested portions of the register, the command received from the guest software is executed on the requested portions of the register.

公开(公告)号：US06996748B2

公开(公告)日：2006-02-07

申请号：US10184798

申请日：2002-06-29

申请人： Richard Uhlig ,  Andrew V. Anderson ,  Steve Bennett ,  Erik Cota-Robles ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Gilbert Neiger

发明人： Richard Uhlig ,  Andrew V. Anderson ,  Steve Bennett ,  Erik Cota-Robles ,  Stalinselvaraj Jeyasingh ,  Alain Kagi ,  Gilbert Neiger

IPC分类号： G06F11/00

CPC分类号： G06F11/0712 ,  G06F11/0751

摘要： In one embodiment, fault information relating to a fault associated with the operation of guest software is received. Further, a determination is made as to whether the fault information satisfies one or more fault filtering criteria. If the determination is positive, the guest software is permitted to disregard the fault.

摘要翻译： 在一个实施例中，接收到与客户软件的操作相关联的故障的故障信息。 此外，确定故障信息是否满足一个或多个故障过滤标准。 如果确定是肯定的，则客户软件被允许忽略该故障。

公开(公告)号：US10515023B2

公开(公告)日：2019-12-24

申请号：US15088739

申请日：2016-04-01

申请人： Ravi L. Sahita ,  Gilbert Neiger ,  Vedvyas Shanbhogue ,  David M. Durham ,  Andrew V. Anderson ,  David A. Koufaty ,  Asit K. Mallick ,  Arumugam Thiyagarajah ,  Barry E. Huntley ,  Deepak K. Gupta ,  Michael Lemay ,  Joseph F. Cihula ,  Baiju V. Patel

发明人： Ravi L. Sahita ,  Gilbert Neiger ,  Vedvyas Shanbhogue ,  David M. Durham ,  Andrew V. Anderson ,  David A. Koufaty ,  Asit K. Mallick ,  Arumugam Thiyagarajah ,  Barry E. Huntley ,  Deepak K. Gupta ,  Michael Lemay ,  Joseph F. Cihula ,  Baiju V. Patel

IPC分类号： G06F12/00 ,  G06F12/14 ,  G06F12/1009 ,  G06F9/455 ,  G06F12/1027 ,  G06F21/78

摘要： This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.

公开(公告)号：US09916257B2

公开(公告)日：2018-03-13

申请号：US13191327

申请日：2011-07-26

申请人： Rajesh M. Sankaran ,  Altug Koker ,  Philip R. Lantz ,  Asit K. Mallick ,  James B. Crossland ,  Aditya Navale ,  Gilbert Neiger ,  Andrew V. Anderson

发明人： Rajesh M. Sankaran ,  Altug Koker ,  Philip R. Lantz ,  Asit K. Mallick ,  James B. Crossland ,  Aditya Navale ,  Gilbert Neiger ,  Andrew V. Anderson

IPC分类号： G06F12/10 ,  G06F12/1027 ,  G06F12/1081

CPC分类号： G06F12/1027 ,  G06F12/1081 ,  G06F2212/1016 ,  G06F2212/1048 ,  G06F2212/303 ,  G06F2212/682 ,  G06F2212/683

摘要： Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.