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    METHOD AND APPARATUS FOR TLB SHOOT-DOWN IN A HETEROGENEOUS COMPUTING SYSTEM SUPPORTING SHARED VIRTUAL MEMORY
    1.
    发明申请
    METHOD AND APPARATUS FOR TLB SHOOT-DOWN IN A HETEROGENEOUS COMPUTING SYSTEM SUPPORTING SHARED VIRTUAL MEMORY 有权
    支持共享虚拟内存的异构计算系统中TLB SHOOT-DOWN的方法和设备

    公开(公告)号：US20130031333A1

    公开(公告)日：2013-01-31

    申请号：US13191327

    申请日：2011-07-26

    申请人： Rajesh M. Sankaran ,  Altug Koker ,  Philip R. Lantz ,  Asit K. Mallick ,  James B. Crossland ,  Aditya Navale ,  Gilbert Neiger ,  Andrew V. Anderson

    发明人： Rajesh M. Sankaran ,  Altug Koker ,  Philip R. Lantz ,  Asit K. Mallick ,  James B. Crossland ,  Aditya Navale ,  Gilbert Neiger ,  Andrew V. Anderson

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1027 ,  G06F12/1081 ,  G06F2212/1016 ,  G06F2212/1048 ,  G06F2212/303 ,  G06F2212/682 ,  G06F2212/683

    摘要： Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.

    摘要翻译： 公开了用于在多核系统中共享虚拟存储器的异构设备的有效TLB（转换后备缓冲器）击穿的方法和装置。 用于有效的TLB击倒的装置的实施例可以包括用于存储虚拟地址转换条目的TLB和与TLB耦合的存储器管理单元，以维护对应于虚拟地址转换条目的PASID（进程地址空间标识符）状态条目 。 PASID状态条目可以包括活动参考状态和惰性无效状态。 响应于从多核系统中的设备接收到PASID状态更新请求并且读取PASID状态条目的惰性无效状态，存储器管理单元可执行PASID状态条目的原子修改。 存储器管理单元可以在响应于相应的惰性无效化状态的激活之前向设备发送PASID状态更新响应以同步TLB条目。

    SYSTEM, APPARATUS, AND METHOD FOR SEGMENT REGISTER READ AND WRITE REGARDLESS OF PRIVILEGE LEVEL
    8.
    发明申请
    SYSTEM, APPARATUS, AND METHOD FOR SEGMENT REGISTER READ AND WRITE REGARDLESS OF PRIVILEGE LEVEL 有权
    系统，设备和分段注册读取和写入权限的优先权级别

    公开(公告)号：US20120166767A1

    公开(公告)日：2012-06-28

    申请号：US12976981

    申请日：2010-12-22

    申请人： Baiju V. Patel ,  Gilbert Neiger ,  Martin G. Dixon ,  James S. Coke ,  James B. Crossland

    发明人： Baiju V. Patel ,  Gilbert Neiger ,  Martin G. Dixon ,  James S. Coke ,  James B. Crossland

    IPC分类号： G06F9/312

    CPC分类号： G06F9/30032 ,  G06F9/30101 ,  G06F9/342

    摘要： Embodiments of systems, apparatuses, and methods for performing privilege agnostic segment base register read or write instruction are described. An exemplary method may include fetching the privilege agnostic segment base register write instruction, wherein the privilege agnostic write instruction includes a 64-bit data source operand, decoding the fetched privilege agnostic segment base register write instruction, and executing the decoded privilege agnostic segment base register write instruction to write the 64-bit data of the source operand into the segment base register identified by the opcode of the privilege agnostic segment base register write instruction.

    摘要翻译： 描述用于执行特权不可知段段基址寄存器读或写指令的系统，装置和方法的实施例。 一种示例性方法可以包括获取特权不可知段基址寄存器写指令，其中特权不可知写指令包括64位数据源操作数，对获取的特权不可知段基址寄存器写指令进行解码，以及执行解码的特权不可知段基址寄存器 写指令将源操作数的64位数据写入由特权不可知段基址寄存器写指令的操作码标识的段基寄存器中。

    System, apparatus, and method for segment register read and write regardless of privilege level
    10.
    发明授权
    System, apparatus, and method for segment register read and write regardless of privilege level 有权
    用于段寄存器读写的系统，设备和方法，无论权限级别如何

    公开(公告)号：US08938606B2

    公开(公告)日：2015-01-20

    申请号：US12976981

    申请日：2010-12-22

    申请人： Baiju V. Patel ,  Gilbert Neiger ,  Martin G. Dixon ,  James S. Coke ,  James B. Crossland

    发明人： Baiju V. Patel ,  Gilbert Neiger ,  Martin G. Dixon ,  James S. Coke ,  James B. Crossland

    IPC分类号： G06F9/30 ,  G06F9/34

    CPC分类号： G06F9/30032 ,  G06F9/30101 ,  G06F9/342

    摘要： Embodiments of systems, apparatuses, and methods for performing privilege agnostic segment base register read or write instruction are described. An exemplary method may include fetching the privilege agnostic segment base register write instruction, wherein the privilege agnostic write instruction includes a 64-bit data source operand, decoding the fetched privilege agnostic segment base register write instruction, and executing the decoded privilege agnostic segment base register write instruction to write the 64-bit data of the source operand into the segment base register identified by the opcode of the privilege agnostic segment base register write instruction.

    摘要翻译： 描述用于执行特权不可知段段基址寄存器读或写指令的系统，装置和方法的实施例。 一种示例性方法可以包括获取特权不可知段基址寄存器写指令，其中特权不可知写指令包括64位数据源操作数，对获取的特权不可知段基址寄存器写指令进行解码，以及执行解码的特权不可知段基址寄存器 写指令将源操作数的64位数据写入由特权不可知段基址寄存器写指令的操作码标识的段基寄存器中。