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    Reducing energy consumption of set associative caches by reducing checked ways of the set association
    72.
    发明授权
    Reducing energy consumption of set associative caches by reducing checked ways of the set association 失效
    通过减少集合关联的检查方式来减少集合关联缓存的能量消耗

    公开(公告)号：US08341355B2

    公开(公告)日：2012-12-25

    申请号：US12787122

    申请日：2010-05-25

    申请人： Jian Li ,  William E. Speight ,  Lixin Zhang

    发明人： Jian Li ,  William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0864 ,  G06F12/0842 ,  G06F2212/1028 ,  G06F2212/6042 ,  G06F2212/6082 ,  Y02D10/13

    摘要： Mechanisms for accessing a set associative cache of a data processing system are provided. A set of cache lines, in the set associative cache, associated with an address of a request are identified. Based on a determined mode of operation for the set, the following may be performed: determining if a cache hit occurs in a preferred cache line without accessing other cache lines in the set of cache lines; retrieving data from the preferred cache line without accessing the other cache lines in the set of cache lines, if it is determined that there is a cache hit in the preferred cache line; and accessing each of the other cache lines in the set of cache lines to determine if there is a cache hit in any of these other cache lines only in response to there being a cache miss in the preferred cache line(s).

    摘要翻译： 提供了访问数据处理系统的集合关联缓存的机制。 识别与集合关联高速缓存中的与请求的地址相关联的一组高速缓存行。 基于针对集合的确定的操作模式，可以执行以下操作：确定高速缓存命中是否发生在优选高速缓存行中，而不访问该组高速缓存行中的其他高速缓存行; 如果确定在所述优选高速缓存行中存在高速缓存命中，则从所述优选高速缓存行中检索数据而不访问所述一组高速缓存行中的其它高速缓存行; 以及访问该组高速缓存行中的每个其它高速缓存行，以仅在响应于优选高速缓存行中存在高速缓存未命中时确定在这些其它高速缓存行中的任何一个中是否存在高速缓存命中。

    Cache directed sequential prefetch
    75.
    发明授权
    Cache directed sequential prefetch 失效
    缓存定向顺序预取

    公开(公告)号：US07958317B2

    公开(公告)日：2011-06-07

    申请号：US12185219

    申请日：2008-08-04

    申请人： William E. Speight ,  Lixin Zhang

    发明人： William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0862 ,  G06F2212/6026

    摘要： A technique for performing stream detection and prefetching within a cache memory simplifies stream detection and prefetching. A bit in a cache directory or cache entry indicates that a cache line has not been accessed since being prefetched and another bit indicates the direction of a stream associated with the cache line. A next cache line is prefetched when a previously prefetched cache line is accessed, so that the cache always attempts to prefetch one cache line ahead of accesses, in the direction of a detected stream. Stream detection is performed in response to load misses tracked in the load miss queue (LMQ). The LMQ stores an offset indicating a first miss at the offset within a cache line. A next miss to the line sets a direction bit based on the difference between the first and second offsets and causes prefetch of the next line for the stream.

    摘要翻译： 用于在高速缓冲存储器内执行流检测和预取的技术简化了流检测和预取。 高速缓存目录或高速缓存条目中的一点表示高速缓存行未被访问，并且另一位指示与高速缓存行相关联的流的方向。 当先前预取的高速缓存行被访问时，预取下一个高速缓存行，使得高速缓存总是尝试在检测到的流的方向上预取访问之前的一个高速缓存行。 响应于在负载未命中队列（LMQ）中跟踪的加载未命中，执行流检测。 LMQ存储指示高速缓存行内的偏移处的第一个未命中的偏移。 下一个未命中的线路将基于第一和第二个偏移量之间的差异设置方向位，并导致流的下一行的预取。

    CACHE DIRECTED SEQUENTIAL PREFETCH
    76.
    发明申请
    CACHE DIRECTED SEQUENTIAL PREFETCH 失效
    高速缓存指令序列预选

    公开(公告)号：US20100030973A1

    公开(公告)日：2010-02-04

    申请号：US12185219

    申请日：2008-08-04

    申请人： William E. Speight ,  Lixin Zhang

    发明人： William E. Speight ,  Lixin Zhang

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0862 ,  G06F2212/6026

    摘要： A technique for performing stream detection and prefetching within a cache memory simplifies stream detection and prefetching. A bit in a cache directory or cache entry indicates that a cache line has not been accessed since being prefetched and another bit indicates the direction of a stream associated with the cache line. A next cache line is prefetched when a previously prefetched cache line is accessed, so that the cache always attempts to prefetch one cache line ahead of accesses, in the direction of a detected stream. Stream detection is performed in response to load misses tracked in the load miss queue (LMQ). The LMQ stores an offset indicating a first miss at the offset within a cache line. A next miss to the line sets a direction bit based on the difference between the first and second offsets and causes prefetch of the next line for the stream.

    摘要翻译： 用于在高速缓冲存储器内执行流检测和预取的技术简化了流检测和预取。 高速缓存目录或高速缓存条目中的一点表示高速缓存行未被访问，并且另一位指示与高速缓存行相关联的流的方向。 当先前预取的高速缓存行被访问时，预取下一个高速缓存行，使得高速缓存总是尝试在检测到的流的方向上预取访问之前的一个高速缓存行。 响应于在负载未命中队列（LMQ）中跟踪的加载未命中，执行流检测。 LMQ存储指示高速缓存行内的偏移处的第一个未命中的偏移。 下一个未命中的线路将基于第一和第二个偏移量之间的差异设置方向位，并导致流的下一行的预取。

    Method and device for determining forwarding rule for data packet
    77.
    发明授权
    Method and device for determining forwarding rule for data packet 有权
    确定数据包转发规则的方法和装置

    公开(公告)号：US09197550B2

    公开(公告)日：2015-11-24

    申请号：US13513959

    申请日：2009-12-17

    申请人： Lixin Zhang ,  Duan Chen ,  Lijun Chen

    发明人： Lixin Zhang ,  Duan Chen ,  Lijun Chen

    IPC分类号： H04L12/28 ,  H04L12/723 ,  H04L12/46 ,  H04L12/721

    CPC分类号： H04L45/50 ,  H04L12/4625 ,  H04L12/4641 ,  H04L45/66 ,  H04L45/68

    摘要： A method and corresponding device for determining forwarding rule for data packet in Virtual Private LAN Service with Provider Backbone Bridge (PBB-VPLS) network are disclosed. In the method, a value in a backbone service instance identifier (I-SID) field of the received data packet is firstly examined, then a virtual split horizon group corresponding to the data packets is determined based on the I-SID value, wherein the virtual split horizon group defines a forwarding rule for the data packets between different pseudo wire ports of the PBB-VPLS network. With the dynamic split horizon group, the method dynamically adapts to different forwarding rules for multiple I-VPLS instances with different tree topologies, and is capable of supporting multiple I-VPLS instances with different root sites and tree topologies in one B-VPLS instance, thereby ensuring the stability of the backbone network and reducing the network operation cost.

    摘要翻译： 公开了一种用于确定具有提供商骨干桥（PBB-VPLS）网络的虚拟专用LAN服务中的数据分组的转发规则的方法和相应设备。 在该方法中，首先检查接收到的数据分组的骨干服务实例标识符（I-SID）字段中的值，然后基于I-SID值确定与数据分组对应的虚拟水平分割组，其中， 虚拟水平分割组为PBB-VPLS网络的不同伪线端口之间的数据包定义了转发规则。 利用动态水平分割组，该方法动态适应不同树拓扑的多个I-VPLS实例的不同转发规则，并且能够在一个B-VPLS实例中支持具有不同根站点和树形拓扑的多个I-VPLS实例， 从而确保骨干网的稳定性，降低网络运营成本。

    Termination for superjunction VDMOSFET
    78.
    发明授权
    Termination for superjunction VDMOSFET 有权
    端接VDMOSFET

    公开(公告)号：US08482064B2

    公开(公告)日：2013-07-09

    申请号：US13493505

    申请日：2012-06-11

    申请人： Yangbo Yi ,  Haisong Li ,  Qin Wang ,  Ping Tao ,  Lixin Zhang

    发明人： Yangbo Yi ,  Haisong Li ,  Qin Wang ,  Ping Tao ,  Lixin Zhang

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696

    摘要： A termination for silicon superjunction VDMOSFET comprises heavily doped N-type silicon substrate which also works as drain region; drain metal is disposed on the back surface of the heavily doped N-type silicon substrate; an N-type silicon epitaxial layer is disposed on the heavily doped N-type silicon substrate; P-type silicon columns and N-type silicon columns are formed in the N-type silicon epitaxial layer, alternately arranged; a continuous silicon oxide layer is disposed on a part of silicon surface in the termination; structures that block the drift of mobile ions (several discontinuous silicon oxide layers arranged at intervals) are disposed on the other part of silicon surface in the termination. The structures that block the drift of mobile ions disposed in the termination region are able to effectively prevent movement of the mobile ions and improve the capability of the power device against the contamination induced by the mobile ions.

    摘要翻译： 硅超结VDMOSFET的终端包括也用作漏极区的重掺杂N型硅衬底; 漏极金属配置在重掺杂N型硅衬底的背表面上; 在重掺杂的N型硅衬底上设置N型硅外延层; 交替布置在N型硅外延层中形成P型硅柱和N型硅柱; 连续的氧化硅层设置在终端的硅表面的一部分上; 阻止移动离子漂移的结构（间隔布置的几个不连续的氧化硅层）设置在终端的硅表面的另一部分上。 阻止设置在终端区域中的移动离子的漂移的结构能够有效地防止移动离子的移动，并提高功率器件抵抗由移动离子引起的污染的能力。

    Indexed table circuit having reduced aliasing
    80.
    发明授权
    Indexed table circuit having reduced aliasing 有权
    索引表电路具有减少的混叠

    公开(公告)号：US08086831B2

    公开(公告)日：2011-12-27

    申请号：US12024241

    申请日：2008-02-01

    申请人： Lei Chen ,  Lixin Zhang

    发明人： Lei Chen ,  Lixin Zhang

    IPC分类号： G06F9/35 ,  G06F9/355

    CPC分类号： G06F9/3848

    摘要： In at least one embodiment, an indexed table circuit includes a plurality of banks for storing data to be accessed and a split index array. The indexed table circuit is organized in a plurality of entries each corresponding to a respective one of a plurality of different entry indices, where each entry includes a storage location in the plurality of banks and the split index array. The indexed table circuit further includes selection logic that, responsive to read access of an entry among the plurality of entries utilizing an entry index of a bit string, utilizes a split index read from the split index array to select a set of one or more bits of a tag of the bit string, utilizes the selected set of one or more bits to select data read from one of the plurality of banks, and outputs the selected data.

    摘要翻译： 在至少一个实施例中，索引表电路包括用于存储要访问的数据的多个存储体和分离索引阵列。 索引表电路被组织成多个条目，每个条目对应于多个不同入口索引中的相应一个，其中每个条目包括多个存储体中的存储位置和拆分索引阵列。 索引表电路还包括选择逻辑，其响应于使用位串的条目索引的多个条目中的条目的读取访问，利用从拆分索引数组读取的拆分索引来选择一个或多个位的集合 使用所选择的一个或多个位的集合来选择从多个存储体之一读取的数据，并输出所选择的数据。