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95 条记录 (耗时 0.042 秒)

    Self-healing chip-to-chip interface
    71.
    发明授权
    Self-healing chip-to-chip interface 失效
    自愈芯片到芯片的接口

    公开(公告)号：US08018837B2

    公开(公告)日：2011-09-13

    申请号：US12635121

    申请日：2009-12-10

    申请人： Wiren D. Becker ,  Daniel M. Dreps ,  Frank D. Ferraiolo ,  Anand Haridass ,  Robert J. Reese

    发明人： Wiren D. Becker ,  Daniel M. Dreps ,  Frank D. Ferraiolo ,  Anand Haridass ,  Robert J. Reese

    IPC分类号： G01R31/08

    CPC分类号： H01L22/22 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

    摘要翻译： 一种用于管理用于芯片的一组信号路径的方法，装置和计算机指令。 检测用于芯片的信号路径集合内的有缺陷的信号路径。 信号通过一组信号路径重新路由，使得有缺陷的信号路径从信号路径集合中移除，并使用信号路径组中的剩余数据信号路径发送信号，并且响应于检测到的信号路径 有缺陷的信号路径。

    Dynamic segment sparing and repair in a memory system
    72.
    发明授权
    Dynamic segment sparing and repair in a memory system 失效
    内存系统中的动态段保存和修复

    公开(公告)号：US07895374B2

    公开(公告)日：2011-02-22

    申请号：US12165809

    申请日：2008-07-01

    申请人： Frank D. Ferraiolo ,  Ravi K. Arimilli ,  Daniel M. Dreps ,  Kevin C. Gower ,  Robert J. Reese

    发明人： Frank D. Ferraiolo ,  Ravi K. Arimilli ,  Daniel M. Dreps ,  Kevin C. Gower ,  Robert J. Reese

    IPC分类号： G06F3/00 ,  G06F13/00

    CPC分类号： G06F13/4243 ,  G06F11/2007 ,  G06F11/2017 ,  Y02D10/14 ,  Y02D10/151

    摘要： A communication interface device, system, method, and design structure for providing dynamic segment sparing and repair in a memory system. The communication interface device includes drive-side switching logic including driver multiplexers to select driver data for transmitting on link segments of a bus, and receive-side switching logic including receiver multiplexers to select received data from the link segments of the bus. The bus includes multiple data link segments, a clock link segment, and at least two spare link segments selectable by the drive-side switching logic and the receive-side switching logic to replace one or more of the data link segments and the clock link segment.

    摘要翻译： 用于在存储器系统中提供动态段保存和修复的通信接口设备，系统，方法和设计结构。 通信接口装置包括驱动侧切换逻辑，包括驱动器多路复用器，用于选择用于在总线的链路段上发送的驱动器数据，以及包括接收机多路复用器的接收侧切换逻辑，以从总线的链路段选择接收的数据。 该总线包括多个数据链路段，一个时钟链路段，以及由驱动器侧切换逻辑和接收侧切换逻辑选择的至少两个备用链路段，用于替换一个或多个数据链路段和时钟链路段 。

    CONVECTION OVEN
    73.
    发明申请
    CONVECTION OVEN 有权
    对流恒温烤箱

    公开(公告)号：US20100301034A1

    公开(公告)日：2010-12-02

    申请号：US12841393

    申请日：2010-07-22

    申请人： Jack Greenwood ,  Robert J. Reese

    发明人： Jack Greenwood ,  Robert J. Reese

    IPC分类号： A21B1/00

    CPC分类号： F24C15/327 ,  A21B1/26 ,  A21D8/06 ,  F24C7/006 ,  F24C7/082

    摘要： A convection oven having a vapor collection system; water injection system; easily accessible electrical components; and a variable-speed, reversible blower is disclosed. The vapor collection system collects vapor from the cooking chamber during a cooking event, condenses the vapor, and drains the condensed vapor. The water injection system injects water for impact against a blower wheel for dispersion into the air circulating through the cooking chamber. The electrical components are housed within a housing that in a closed position conceals the components and in a closed position exposes the components for easy access. The rotational speed and direction of the variable-speed, reversible blower is controlled during a cooking event according to predetermined speed curves which may include one or more reversal events to achieve more uniform cooking of food. A main controller is programmable via an operator input (e.g., liquid crystal display touch screen) to control operating parameters of the oven.

    摘要翻译： 一种具有蒸气收集系统的对流烘箱; 注水系统; 易于接近的电气元件; 并且公开了一种可变速度的可逆鼓风机。 蒸气收集系统在烹饪事件期间从烹饪室收集蒸气，冷凝蒸气并排出冷凝的蒸气。 注水系统将水冲击到鼓风机轮上，以分散到通过烹饪室循环的空气中。 电气部件容纳在壳体内，该壳体处于闭合位置，隐藏部件并且在关闭位置使部件暴露以便于接近。 根据可能包括一个或多个反转事件的预定速度曲线在烹饪事件期间控制可变速可逆式鼓风机的转速和方向，以实现食物的更均匀的烹饪。 主控制器可通过操作员输入（例如，液晶显示器触摸屏）来编程，以控制烘箱的操作参数。

    BIT SHADOWING IN A MEMORY SYSTEM
    74.
    发明申请
    BIT SHADOWING IN A MEMORY SYSTEM 失效
    记忆系统中的位冲突

    公开(公告)号：US20100005345A1

    公开(公告)日：2010-01-07

    申请号：US12165799

    申请日：2008-07-01

    申请人： Frank D. Ferraiolo ,  Daniel M. Dreps ,  Kevin C. Gower ,  Robert J. Reese

    发明人： Frank D. Ferraiolo ,  Daniel M. Dreps ,  Kevin C. Gower ,  Robert J. Reese

    IPC分类号： G06F11/00

    CPC分类号： G06F11/167 ,  G06F11/073 ,  G06F11/076 ,  G06F11/1004 ,  G06F11/2007 ,  G11C5/04 ,  G11C29/02 ,  G11C29/022

    摘要： A communication interface device, system, method, and design structure for bit shadowing in a memory system are provided. The communication interface device includes shadow selection logic to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. The communication interface device also includes shadow compare logic to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.

    摘要翻译： 提供了一种用于存储器系统中的位阴影的通信接口设备，系统，方法和设计结构。 通信接口设备包括用于选择驱动器位位置作为阴影驱动器值的阴影选择逻辑，以及线驱动器，以在总线的单独链路段上传送所选择的驱动器位位置和阴影驱动器值的数据。 通信接口设备还包括阴影比较逻辑，以将所选择的接收值与来自总线的阴影接收值进行比较，并且识别响应于比较不匹配的错误比较，以及阴影计数器来计数相对于总线的误比率 错误率在一段时间内。 响应于在总线错误率的预定阈值内的错误比较的速率来识别有缺陷的链路段。

    Arrangements for Operating In-Line Memory Module Configurations
    75.
    发明申请
    Arrangements for Operating In-Line Memory Module Configurations 审中-公开
    操作串行内存模块配置的安排

    公开(公告)号：US20090276559A1

    公开(公告)日：2009-11-05

    申请号：US12114533

    申请日：2008-05-02

    申请人： James J. Allen, JR. ,  Robert J. Reese ,  Michael B. Spear ,  Peter M. Thomsen ,  Michael R. Trombley

    发明人： James J. Allen, JR. ,  Robert J. Reese ,  Michael B. Spear ,  Peter M. Thomsen ,  Michael R. Trombley

    IPC分类号： G06F12/06

    CPC分类号： G06F13/1684 ,  G06F13/161

    摘要： In one embodiment, a method is disclosed for timing responses to a plurality of memory requests. The method can include sending a plurality of memory requests to a plurality of in-line memory modules. The requests can be sent over a channel from a plurality of channels, where each channel can have a plurality of lanes. The method can receive responses to the plurality of memory requests over the channel and monitor the response to detect a timing relationship between at least two lanes from the plurality of lanes. In addition, the method can adjust a timing of a register loading and unloading sequence in response to the monitoring of multiple lanes and channels. Other embodiments are also disclosed.

    摘要翻译： 在一个实施例中，公开了一种用于对多个存储器请求进行定时响应的方法。 该方法可以包括向多个在线存储器模块发送多个存储器请求。 可以通过信道从多个信道发送请求，其中每个信道可以具有多个通道。 该方法可以通过信道接收对多个存储器请求的响应，并监视响应以检测来自多个车道的至少两个车道之间的定时关系。 此外，该方法可以响应于多个通道和通道的监视来调整寄存器加载和卸载序列的定时。 还公开了其他实施例。

    Content adaptive variable length coding (CAVLC) decoding
    76.
    发明授权
    Content adaptive variable length coding (CAVLC) decoding 失效
    内容自适应可变长度编码（CAVLC）解码

    公开(公告)号：US07602850B2

    公开(公告)日：2009-10-13

    申请号：US10741233

    申请日：2003-12-19

    申请人： Robert J. Reese

    发明人： Robert J. Reese

    IPC分类号： H04N7/12 ,  G06K9/36

    CPC分类号： H03M7/42 ,  H04N19/136 ,  H04N19/184 ,  H04N19/42 ,  H04N19/44 ,  H04N19/61 ,  H04N19/91

    摘要： A method and apparatus for decoding a bitstream. The method may include generating an indication of a number of coefficients and a number of trailing ones in a portion of a bitstream using either a first lookup table (LUT) indexed by a number of leading zeros to return a number of remaining bits in a code and a second LUT indexed by both the number of leading zeros and the remaining code bits to return the number of coefficients and the number of trailing ones or bit parsing processing when the leading zeros value equals a predetermined value, generating an indication of a number of total zeros, including using either a third LUT indexed by the number of coefficients and bits of the bitstream when the number of coefficients is in a first range or bit level processing when the number of coefficients is outside the first range, generating an indication of one or more run before values using either a fourth LUT indexed by the number of coefficients and bits of the bitstream when a zeros left value is in a second range or bit parsing processing when the zeros left is not in the second range, and generating coefficients in block positions in response to the generation of the trailing ones value, the number of coefficients value, the total zeros value and run before values.

    摘要翻译： 一种用于对比特流进行解码的方法和装置。 该方法可以包括使用由多个前导零索引的第一查找表（LUT）生成比特流的一部分中的系数数量和尾数的数量的指示，以返回码中的剩余比特数 以及当前导零值等于预定值时由前导零的数量和剩余码位两者索引的第二LUT，用于返回系数的数量和尾随的数量或位解析处理，生成多个 全零，包括当系数数目处于第一范围时使用由系数数和索引索引的第三LUT，当系数数量超出第一范围时，产生一个指示 或更多的值在使用由第零个范围内的零的系数和比特数的索引索引的第四个LUT或第二个范围的位解析时运行 当零离开不在第二范围时停止，并且响应于后一个值的生成，系数值的数量，总零值和运行的值，生成块位置中的系数。

    Image edge filtering
    77.
    发明授权
    Image edge filtering 失效
    图像边缘滤波

    公开(公告)号：US07551322B2

    公开(公告)日：2009-06-23

    申请号：US10880977

    申请日：2004-06-29

    申请人： Robert J. Reese

    发明人： Robert J. Reese

    IPC分类号： G06K15/00 ,  G06K9/40

    CPC分类号： G06T5/002 ,  G06T2200/28 ,  G06T2207/20021

    摘要： Techniques for image edge filter processing are provided. Data samples surrounding vertical and horizontal edges of an image are acquired and iteratively processed. If the samples are associated with vertical edges, the data associated with the samples are transposed prior to applying a selected filter. The samples are stored in two buffers (one buffer for each unique side of an edge being processed) and selective filters applied thereon. Each sample set includes more than four samples of data. Once the filters are processed, the data in the buffers is written as portions of a modified image. If the samples were associated with vertical edges, then the data is re-transposed out of the buffers as it is written.

    摘要翻译： 提供了图像边缘滤波处理技术。 获取并迭代地处理围绕图像的垂直和水平边缘的数据样本。 如果样本与垂直边缘相关联，则在应用选定的滤波器之前，将与样本相关联的数据转置。 样品存储在两个缓冲器中（一个缓冲区用于正在处理的边缘的每个独特侧）和选择性滤波器。 每个样本集包括四个以上的数据样本。 一旦处理过滤器，缓冲器中的数据被写入修改后的图像的部分。 如果样本与垂直边缘相关联，则数据在写入缓冲区时被重新转置。

    Elastic interface de-skew mechanism
    78.
    发明授权
    Elastic interface de-skew mechanism 有权
    弹性界面去歪斜机制

    公开(公告)号：US07461287B2

    公开(公告)日：2008-12-02

    申请号：US11055866

    申请日：2005-02-11

    申请人： Daniel M. Dreps ,  Frank D. Ferraiolo ,  Gary A. Peterson ,  Robert J. Reese

    发明人： Daniel M. Dreps ,  Frank D. Ferraiolo ,  Gary A. Peterson ,  Robert J. Reese

    IPC分类号： G06F1/04 ,  G06F13/42

    CPC分类号： G06F5/06 ,  G06F1/10

    摘要： A mechanism for de-skewing and aligning data bits sent between two chips on an elastic interface. On the receiving end of an elastic interface, the eye of each data bit within a clock/data group is delayed by less than a bit time to align the eyes with the nearest clock edge of a received clock signal. In addition to aligning the eyes of the individual data bits with the nearest clock edge, IAP patterns are used to determine the amount of further delay needed to line up the individual data beats from each data bit. If the data beats for the data bits are not aligned, all but the slowest data beat are delayed to align the data beats for all bits. The additional delay is achieved using sample latches that result in a delayed signal with less jitter. As a result of having less jitter, the received, de-skewed, and aligned clock/data group can be forwarded to the operative portion of the receiving chip at an increased frequency.

    摘要翻译： 用于在弹性界面上在两个芯片之间发送的数据位的偏斜和对准的机制。 在弹性接口的接收端，时钟/数据组内的每个数据位的眼睛被延迟小于一点时间，以使眼睛与接收到的时钟信号的最近的时钟沿对齐。 除了将各个数据位的眼睛与最近的时钟边沿对齐之外，还使用IAP模式来确定从每个数据位排列各个数据节拍所需的进一步延迟量。 如果数据位的数据跳转不对齐，除了最慢的数据跳转之外，除了所有位的数据跳转之外，都会被延迟。 使用采样锁存器实现额外的延迟，导致延迟信号抖动较小。 由于具有较少的抖动，所接收的，去偏斜的和对准的时钟/数据组可以以增加的频率转发到接收芯片的操作部分。