公开(公告)号：US08060027B2

公开(公告)日：2011-11-15

申请号：US12721930

申请日：2010-03-11

申请人： Khurram Muhammad ,  Dirk Leipold

发明人： Khurram Muhammad ,  Dirk Leipold

IPC分类号： H04B1/38

CPC分类号： H03C5/00 ,  H04B1/525 ,  H04B1/707

摘要： The present invention provides an RF transmission leakage mitigator for use with a full-duplex, wireless transceiver. In one embodiment, the RF transmission leakage mitigator includes an inversion generator configured to provide an RF transmission inversion signal of an interfering transceiver RF transmission to a receiving portion of the transceiver thereby creating a residual leakage signal. Additionally, the RF transmission leakage mitigator also includes a residual processor coupled to the inversion generator and configured to adjust the RF transmission inversion signal of the interfering transceiver RF transmission based on reducing the residual leakage signal to a specified level.

摘要翻译： 本发明提供了一种与全双工无线收发器一起使用的RF传输泄漏缓解器。 在一个实施例中，RF传输泄漏减轻器包括反相发生器，其被配置为将干扰收发器RF传输的RF发射反转信号提供给收发器的接收部分，从而产生残余泄漏信号。 此外，RF传输泄漏缓解器还包括耦合到反向发生器并被配置为基于将剩余泄漏信号减小到指定电平来调整干扰收发器RF传输的RF发射反转信号的残余处理器。

公开(公告)号：US20090207940A1

公开(公告)日：2009-08-20

申请号：US12432447

申请日：2009-04-29

申请人： Robert Bogdan Staszewski ,  Dirk Leipold

发明人： Robert Bogdan Staszewski ,  Dirk Leipold

IPC分类号： H04L25/03 ,  H04L25/49

CPC分类号： H03F1/3282 ,  H03F1/0211 ,  H03F1/3247 ,  H03F2200/331

摘要： Systems and methods are provided for calibrating a digital predistorter in an integrated transceiver circuit. A digital transmitter path provides a signal from a digital input. The transmitter path includes a digital predistorter that predistorts the digital input to mitigate nonlinearities associated with a power amplifier. The integrated transceiver circuit further includes a receiver path associated with the digital transmitter path. A coupling element provides the signal from the transmitter path to the receiver path. A signal evaluator determines values for at least one parameter associated with the digital predistorter based on the signal.

摘要翻译： 提供了用于校准集成收发器电路中的数字预失真器的系统和方法。 数字发射器路径提供来自数字输入的信号。 发射机路径包括数字预失真器，其预失真数字输入以减轻与功率放大器相关联的非线性。 集成收发器电路还包括与数字发送器路径相关联的接收器路径。 耦合元件提供从发射机路径到接收机路径的信号。 信号评估器基于该信号确定与数字预失真器相关联的至少一个参数的值。

公开(公告)号：US20090096525A1

公开(公告)日：2009-04-16

申请号：US12134464

申请日：2008-06-06

申请人： Robert Bogdan Staszewski ,  See Taur Lee ,  Dirk Leipold

发明人： Robert Bogdan Staszewski ,  See Taur Lee ,  Dirk Leipold

IPC分类号： H03F3/21 ,  H03F3/68 ,  H03F1/02

CPC分类号： H03F3/189 ,  H03F3/211 ,  H03F3/602 ,  H03F2200/541

摘要： Methods to implement power control in a digital power amplifier are described.

摘要翻译： 描述了在数字功率放大器中实现功率控制的方法。

公开(公告)号：US20080227424A1

公开(公告)日：2008-09-18

申请号：US11717563

申请日：2007-03-13

申请人： Khurram Muhammad ,  Meng-Chang Lee ,  Dirk Leipold

发明人： Khurram Muhammad ,  Meng-Chang Lee ,  Dirk Leipold

IPC分类号： H04Q7/20 ,  H03M1/12 ,  H04B1/16

CPC分类号： H04B1/28 ,  H03M1/183 ,  H04B1/0007

摘要： Methods and apparatus to perform radio frequency (RF) analog-to-digital conversion are described. According to one example, a receiver includes an amplifier to amplify received analog RF signals and a mixer-free circuit for converting the received analog RF signals to digital signals.

摘要翻译： 描述了执行射频（RF）模数转换的方法和装置。 根据一个示例，接收机包括用于放大接收到的模拟RF信号的放大器和用于将所接收的模拟RF信号转换为数字信号的无混频器电路。

公开(公告)号：US20080157839A1

公开(公告)日：2008-07-03

申请号：US11690506

申请日：2007-03-23

申请人： Robert Bogdan Staszewski ,  Dirk Leipold ,  Wei Chen

发明人： Robert Bogdan Staszewski ,  Dirk Leipold ,  Wei Chen

IPC分类号： H03L7/00

CPC分类号： H03L7/091 ,  H03L2207/50

摘要： A time-to-digital converter (TDC), a system-on-chip including a TDC, a method of phase detection for use in synthesizing a clock signal and a non-linearity corrector for a TDC. In one embodiment, the TDC includes a chain of delay elements configured to receive a clock signal and generate delayed clock signals. Each one of the delay elements includes: (1) a non-inverting buffer configured to delay the clock signal by about twice a delay of an inverter to provide a buffer-delayed clock signal and (2) a first transmission gate coupled to the non-inverting buffer and configured to delay the clock signal by about the delay of an inverter to provide a first gate-delayed clock signal.

摘要翻译： 时间数字转换器（TDC），包括TDC的片上系统，用于合成时钟信号的相位检测方法和用于TDC的非线性校正器。 在一个实施例中，TDC包括被配置为接收时钟信号并产生延迟的时钟信号的延迟元件链。 每个延迟元件包括：（1）非反相缓冲器，被配置为将时钟信号延迟约两倍的逆变器的延迟以提供缓冲器延迟的时钟信号，以及（2）耦合到非反相缓冲器的第一传输门 反相缓冲器并且被配置为将时钟信号延迟大约逆变器的延迟以提供第一门延迟的时钟信号。

公开(公告)号：US07375598B2

公开(公告)日：2008-05-20

申请号：US11009495

申请日：2004-12-10

申请人： Chih-Ming Hung ,  Dirk Leipold ,  Nathen Barton

发明人： Chih-Ming Hung ,  Dirk Leipold ,  Nathen Barton

IPC分类号： H03B5/00

CPC分类号： H03B5/1296 ,  H03B5/1209 ,  H03B5/1256 ,  H03B5/1287

摘要： System and method for increasing the frequency tuning range of a RF/microwave LC oscillator. A preferred embodiment comprises a voltage controlled oscillator (VCO) configured to generate an output signal at a frequency that is dependent upon a magnitude of an input voltage level and an effective inductance of an inductive load and a variable inductor coupled to the VCO. The variable inductor comprises a primary inductor coupled to the VCO to produce a magnetic field based upon a current flowing through the primary inductor and a secondary inductor magnetically coupled to the primary inductor, the secondary inductor to affect the magnitude of the effective inductance of the primary inductor.

摘要翻译： 用于增加RF /微波LC振荡器的频率调谐范围的系统和方法。 优选实施例包括压控振荡器（VCO），其被配置为以取决于输入电压电平的大小和耦合到VCO的电感性负载和可变电感器的有效电感的频率来产生输出信号。 可变电感器包括耦合到VCO的初级电感器，以基于流过初级电感器的电流和与主电感器磁耦合的次级电感器产生磁场，次级电感器影响主电感器的有效电感的幅度 电感。

公开(公告)号：US20060290435A1

公开(公告)日：2006-12-28

申请号：US11464420

申请日：2006-08-14

申请人： Robert Staszewski ,  Dirk Leipold ,  Khurram Muhammad

发明人： Robert Staszewski ,  Dirk Leipold ,  Khurram Muhammad

IPC分类号： H03L7/00

CPC分类号： H03L7/1075 ,  H03F1/0211 ,  H03F1/3282 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/107 ,  H03L2207/50

摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.

摘要翻译： 用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。 优选实施例包括具有比例环路增益路径（比例环路增益电路1115）和积分环路增益模块（积分环路增益模块1120）的环路滤波器。 在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。 然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。 可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。

公开(公告)号：US07003276B2

公开(公告)日：2006-02-21

申请号：US10132025

申请日：2002-04-25

申请人： Khurram Muhammad ,  Dirk Leipold ,  Kenneth J. Maggio

发明人： Khurram Muhammad ,  Dirk Leipold ,  Kenneth J. Maggio

IPC分类号： H04B1/26

CPC分类号： H04B1/0025 ,  H03H15/00 ,  H03H19/004 ,  H04B1/0003 ,  H04B1/28 ,  H04L27/24

摘要： A first periodic voltage waveform (20) is downconverted into a second periodic voltage waveform (35, 36). A plurality of temporally distinct samples (SA1, SA2, . . . ) respectively indicative of areas under corresponding fractional-cycles of the first voltage waveform are obtained. The samples are combined to produce the second voltage waveform. The samples can be manipulated to provide gain adjustment to the second voltage waveform. The samples are obtained by charging a sampling capacitance in response to a current waveform that corresponds to the first voltage waveform. The use of different sampling capacitances during respective predetermined time intervals permits the signal strength of the first waveform to be determined from observation of the second waveform.

摘要翻译： 第一周期性电压波形（20）被下变频成第二周期性电压波形（35,36）。 获得分别表示第一电压波形的相应分数周期下的面积的多个时间上不同的样本（SA 1，SA 2 ...）。 将样品组合以产生第二电压波形。 可以操作样品以对第二电压波形提供增益调整。 通过响应于对应于第一电压波形的电流波形对采样电容进行充电来获得样本。 在各个预定时间间隔期间使用不同的采样电容允许通过观察第二波形来确定第一波形的信号强度。

公开(公告)号：US20050287967A1

公开(公告)日：2005-12-29

申请号：US11115815

申请日：2005-04-26

申请人： Chih-Ming Hung ,  Francis Cruise ,  Dirk Leipold ,  Robert Staszewski

发明人： Chih-Ming Hung ,  Francis Cruise ,  Dirk Leipold ,  Robert Staszewski

IPC分类号： H01Q11/12 ,  H03F1/32 ,  H03F3/191 ,  H04B1/04

CPC分类号： H04B1/0483 ,  H03F1/3241 ,  H03F1/3294 ,  H03F3/191 ,  H03F2200/331

摘要： A novel apparatus for a low noise, high isolation, all digital transmit buffer gain control mechanism. The gain control scheme is presented in the context of an all digital direct digital-to-RF amplitude converter (DRAC), which efficiently combines the traditional transmit chain functions of upconversion, I and Q combining, D/A conversion, filtering, buffering and RF output amplitude control into a single circuit. The transmit buffer is constructed as an array of NMOS switches. The control logic for each NMOS switch comprises a pass-gate type AND gate whose inputs are the phase modulated output of an all digital PLL and the amplitude control word from a digital control block. Power control is accomplished by recognizing the impairments suffered by a pseudo class E pre-power amplifier (PPA) when implemented in a CMOS process. Firstly, the NMOS switches of the array have significant on resistance and thus can only draw a limited current from the an RF choke when the input waveform is high. The significant on resistance of the NMOS switches is exploited in the DRAC circuit to introduce power control of the transmitted waveform and permits a fully digital method of controlling the RF output power.

摘要翻译： 一种低噪声，高隔离，全数字发送缓冲增益控制机制的新型设备。 增益控制方案在全数字直接数/频幅度转换器（DRAC）的上下文中呈现，该转换器有效地结合了上变频，I和Q组合，D / A转换，滤波，缓冲和 RF输出幅度控制成单个电路。 发送缓冲器构造为NMOS开关阵列。 每个NMOS开关的控制逻辑包括一个通门型AND门，其输入是全数字PLL的相位调制输出和来自数字控制块的幅度控制字。 通过在CMOS工艺中实现时，通过识别伪E类预功率放大器（PPA）所遭受的损伤来实现功率控制。 首先，阵列的NMOS开关具有大的导通电阻，因此当输入波形为高时，只能从RF扼流圈画出有限的电流。 在DRAC电路中利用NMOS开关的重要导通电阻来引入发射波形的功率控制，并允许控制RF输出功率的全数字方法。

公开(公告)号：US06963732B2

公开(公告)日：2005-11-08

申请号：US10132436

申请日：2002-04-25

申请人： Khurram Muhammad ,  Dirk Leipold

发明人： Khurram Muhammad ,  Dirk Leipold

IPC分类号： H03H15/00 ,  H03H19/00 ,  H04B1/28 ,  H04B1/707 ,  H04L27/24 ,  H04B1/00

CPC分类号： H03H15/00 ,  H03H19/004 ,  H04B1/0003 ,  H04B1/0025 ,  H04B1/28 ,  H04L27/24

摘要： A first periodic voltage waveform (20) is downconverted into a second periodic voltage waveform (35, 36). A plurality of temporally distinct samples (SA1, SA2, . . . ) respectively indicative of areas under corresponding fractional-cycles of the first voltage waveform are obtained. The samples are combined to produce the second voltage waveform, and are also manipulated to implement a filtering operation such that the second voltage waveform represents a downconverted, filtered version of the first voltage waveform. The second waveform is driven by an amplifier stage (25), and the second waveform can be advantageously constructed so as to permit the amplifier stage to perform internal resets, offset corrections and other ancillary amplifier stage adjustments without losing information in the first waveform.

摘要翻译： 第一周期性电压波形（20）被下变频成第二周期性电压波形（35,36）。 获得分别表示第一电压波形的相应分数周期下的面积的多个时间上不同的样本（SA 1，SA 2 ...）。 将样本组合以产生第二电压波形，并且还被操纵以实现滤波操作，使得第二电压波形表示第一电压波形的下变换的滤波版本。 第二波形由放大器级（25）驱动，并且第二波形可以有利地构造成允许放大器级执行内部复位，偏移校正和其它辅助放大器级调整，而不会丢失第一波形中的信息。