公开(公告)号：US20050287967A1

公开(公告)日：2005-12-29

申请号：US11115815

申请日：2005-04-26

申请人： Chih-Ming Hung ,  Francis Cruise ,  Dirk Leipold ,  Robert Staszewski

发明人： Chih-Ming Hung ,  Francis Cruise ,  Dirk Leipold ,  Robert Staszewski

IPC分类号： H01Q11/12 ,  H03F1/32 ,  H03F3/191 ,  H04B1/04

CPC分类号： H04B1/0483 ,  H03F1/3241 ,  H03F1/3294 ,  H03F3/191 ,  H03F2200/331

摘要： A novel apparatus for a low noise, high isolation, all digital transmit buffer gain control mechanism. The gain control scheme is presented in the context of an all digital direct digital-to-RF amplitude converter (DRAC), which efficiently combines the traditional transmit chain functions of upconversion, I and Q combining, D/A conversion, filtering, buffering and RF output amplitude control into a single circuit. The transmit buffer is constructed as an array of NMOS switches. The control logic for each NMOS switch comprises a pass-gate type AND gate whose inputs are the phase modulated output of an all digital PLL and the amplitude control word from a digital control block. Power control is accomplished by recognizing the impairments suffered by a pseudo class E pre-power amplifier (PPA) when implemented in a CMOS process. Firstly, the NMOS switches of the array have significant on resistance and thus can only draw a limited current from the an RF choke when the input waveform is high. The significant on resistance of the NMOS switches is exploited in the DRAC circuit to introduce power control of the transmitted waveform and permits a fully digital method of controlling the RF output power.

摘要翻译： 一种低噪声，高隔离，全数字发送缓冲增益控制机制的新型设备。 增益控制方案在全数字直接数/频幅度转换器（DRAC）的上下文中呈现，该转换器有效地结合了上变频，I和Q组合，D / A转换，滤波，缓冲和 RF输出幅度控制成单个电路。 发送缓冲器构造为NMOS开关阵列。 每个NMOS开关的控制逻辑包括一个通门型AND门，其输入是全数字PLL的相位调制输出和来自数字控制块的幅度控制字。 通过在CMOS工艺中实现时，通过识别伪E类预功率放大器（PPA）所遭受的损伤来实现功率控制。 首先，阵列的NMOS开关具有大的导通电阻，因此当输入波形为高时，只能从RF扼流圈画出有限的电流。 在DRAC电路中利用NMOS开关的重要导通电阻来引入发射波形的功率控制，并允许控制RF输出功率的全数字方法。

公开(公告)号：US20070008199A1

公开(公告)日：2007-01-11

申请号：US11178993

申请日：2005-07-11

申请人： Sameh Rezeq ,  Dirk Leipold ,  Robert Staszewski ,  Chih-Ming Hung

发明人： Sameh Rezeq ,  Dirk Leipold ,  Robert Staszewski ,  Chih-Ming Hung

IPC分类号： H03M1/06

CPC分类号： H03F1/0205 ,  H03F1/3241 ,  H03F2200/331 ,  H03F2200/375 ,  H03M3/356 ,  H03M3/50 ,  H03M7/3026 ,  H03M7/3037 ,  H04L27/368

摘要： A novel method and apparatus for a negative contributive offset compensation mechanism for a transmit buffer adapted to compensate for the positive offset generated by higher order sigma-delta modulators used to amplitude modulate the transmit buffer. The positive outputs from the sigma-delta modulator are processed differently than the negative outputs. The inverters associated with the negative outputs in the sigma-delta modulator are removed and the clock signal used to drive the transistors corresponding to the negative outputs is negated or shifted 180 degrees from the clock used to drive the transistors corresponding to the positive outputs. A non-inverted version of the clock is used with the positive outputs and an inverse clock is used with the negative outputs. Use of the inverse clock causes a negative contributive offset to be generated that is added on the second half cycle of each clock. The result is an offset compensated RF output signal having zero offset.

摘要翻译： 一种用于发射缓冲器的负贡献偏移补偿机制的新颖方法和装置，适用于补偿由用于幅度调制发射缓冲器的高阶Σ-Δ调制器产生的正偏移。 来自Σ-Δ调制器的正输出的处理方式与负输出不同。 与Σ-Δ调制器中的负输出相关联的反相器被去除，并且用于驱动对应于负输出的晶体管的时钟信号与用于驱动对应于正输出的晶体管的时钟相反或偏移180度。 时钟的非反相版本与正输出一起使用，反时限与负输出一起使用。 使用逆时钟将产生在每个时钟的第二个半周期上添加的负贡献偏移。 结果是具有零偏移的偏移补偿RF输出信号。

公开(公告)号：US20060290435A1

公开(公告)日：2006-12-28

申请号：US11464420

申请日：2006-08-14

申请人： Robert Staszewski ,  Dirk Leipold ,  Khurram Muhammad

发明人： Robert Staszewski ,  Dirk Leipold ,  Khurram Muhammad

IPC分类号： H03L7/00

CPC分类号： H03L7/1075 ,  H03F1/0211 ,  H03F1/3282 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/107 ,  H03L2207/50

摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.

摘要翻译： 用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。 优选实施例包括具有比例环路增益路径（比例环路增益电路1115）和积分环路增益模块（积分环路增益模块1120）的环路滤波器。 在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。 然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。 可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。

公开(公告)号：US20050212606A1

公开(公告)日：2005-09-29

申请号：US11122670

申请日：2005-05-04

申请人： Robert Staszewski ,  Dirk Leipold ,  Khurram Muhammad

发明人： Robert Staszewski ,  Dirk Leipold ,  Khurram Muhammad

IPC分类号： H03F1/02 ,  H03F1/32 ,  H03L7/093 ,  H03L7/099 ,  H03L7/107 ,  H03L7/00

CPC分类号： H03L7/1075 ,  H03F1/0211 ,  H03F1/3282 ,  H03L7/093 ,  H03L7/0991 ,  H03L7/107 ,  H03L2207/50

摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a wireless communication device having a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.

摘要翻译： 用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。 优选实施例包括具有带有比例环路增益路径（比例环路增益电路1115）和积分环路增益块（积分环路增益块1120）的环路滤波器的无线通信设备。 在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。 然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。 可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。

公开(公告)号：US20050130618A1

公开(公告)日：2005-06-16

申请号：US11028995

申请日：2005-01-03

申请人： Robert Staszewski ,  Khurram Muhammad ,  Yo-Chuol Ho ,  Dirk Leipold

发明人： Robert Staszewski ,  Khurram Muhammad ,  Yo-Chuol Ho ,  Dirk Leipold

IPC分类号： H03D7/12 ,  H04B1/10 ,  H04B1/06 ,  H04B7/00 ,  H04L7/00

CPC分类号： H03D7/125 ,  H04B1/1036

摘要： A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having multiple clock generating hardware significantly increases power consumption and integrated circuit area when the mixer 1100 is integrated into silicon. A method and apparatus 1125 containing a circuit for generating a set of clock signals that can be shared by the different signal paths is presented. Advantage is taken of the significant capacitance difference between different sampling capacitors in the mixer and the superposition property.

摘要翻译： 具有多个信号路径的混频器1100通常需要用于每个信号路径的单独的时钟产生硬件。 然而，当混合器1100集成到硅中时，具有多个时钟产生硬件的冗余显着地增加了功耗和集成电路面积。 提出了一种包含用于生成可由不同信号路径共享的一组时钟信号的电路的方法和装置1125。 利用混频器中不同采样电容器之间的显着电容差和叠加特性。

公开(公告)号：US07623838B2

公开(公告)日：2009-11-24

申请号：US11028995

申请日：2005-01-03

申请人： Robert Staszewski ,  Khurram Muhammad ,  Yo-Chuol Ho ,  Dirk Leipold

发明人： Robert Staszewski ,  Khurram Muhammad ,  Yo-Chuol Ho ,  Dirk Leipold

IPC分类号： H04B1/26

CPC分类号： H03D7/125 ,  H04B1/1036

摘要： A mixer 1100 with a plurality of signal paths typically requires separate clock generating hardware for each signal path. However, the redundancy of having multiple clock generating hardware significantly increases power consumption and integrated circuit area when the mixer 1100 is integrated into silicon. A method and apparatus 1125 containing a circuit for generating a set of clock signals that can be shared by the different signal paths is presented. Advantage is taken of the significant capacitance difference between different sampling capacitors in the mixer and the superposition property.

摘要翻译： 具有多个信号路径的混频器1100通常需要用于每个信号路径的单独的时钟产生硬件。 然而，当混合器1100集成到硅中时，具有多个时钟产生硬件的冗余显着地增加了功耗和集成电路面积。 提出了一种包含用于生成可由不同信号路径共享的一组时钟信号的电路的方法和装置1125。 利用混频器中不同采样电容器之间的显着电容差和叠加特性。

公开(公告)号：US20050195917A1

公开(公告)日：2005-09-08

申请号：US10883501

申请日：2004-06-30

申请人： Robert Staszewski ,  Dirk Leipold

发明人： Robert Staszewski ,  Dirk Leipold

IPC分类号： H04L27/04

CPC分类号： H03J7/047 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0966 ,  H03L1/00 ,  H03L2207/50

摘要： A mobile device includes frequency synthesizer circuitry for generating a channel frequency at a multiple of a reference frequency. The reference frequency is generated by a free-running crystal oscillator, without frequency stabilization circuitry. Variations in the output of the crystal oscillator are compensated by adjusting the multiplication factor of the frequency synthesizer.

摘要翻译： 移动设备包括用于以参考频率的倍数产生频道频率的频率合成器电路。 参考频率由自由运行的晶体振荡器产生，没有频率稳定电路。 通过调整频率合成器的乘法因子来补偿晶体振荡器输出的变化。

公开(公告)号：US20050186920A1

公开(公告)日：2005-08-25

申请号：US11062254

申请日：2005-02-18

申请人： Robert Staszewski ,  Dirk Leipold ,  Khurram Muhammad ,  Sameh Rezeq

发明人： Robert Staszewski ,  Dirk Leipold ,  Khurram Muhammad ,  Sameh Rezeq

IPC分类号： H03C3/00 ,  H03L7/16 ,  H04B1/04 ,  H04B1/06 ,  H04B1/68

CPC分类号： H03L7/16 ,  H03L2207/50

摘要： A novel apparatus for and a method of noise and spurious tones suppression in a digital RF processor (DRP). The invention is well suited for use in highly integrated system on a chip (SoC) radio solutions that incorporate a very large amount of digital logic circuitry. The noise suppression scheme eliminates the noise caused by various on chip interference sources transmitted through electromagnetic, power, ground and substrate paths. The noise suppression scheme permits an all digital PLL (ADPLL) to operate in such a way to avoid generating the spurs that would normally be generated from the injection pulling effect of interfering sources on the chip. The frequency reference clock is retimed to be synchronous to the RF oscillator clock and used to drive the entire digital logic circuitry of the DRP. This ensures that the different clock edges throughout the system will not exhibit mutual drift. A method of improving the resolution quality of a time to digital converter within the ADPLL is also taught. The method dithers the reference clock by passing it through a delay circuit that is controlled by a sigma-delta modulator. The dithered reference clock reduces the affect on the phase noise at the output of the ADPLL due to ill-behaved quantization of the TDC timing estimation.

摘要翻译： 一种用于数字RF处理器（DRP）中的噪声和伪噪声抑制的新型装置和方法。 本发明非常适用于结合了大量数字逻辑电路的高度集成的片上系统（SoC）无线电解决方案。 噪声抑制方案消除了通过电磁，电源，接地和基板路径传输的各种片上干扰源引起的噪声。 噪声抑制方案允许所有数字PLL（ADPLL）以这样的方式操作，以避免产生通常由芯片上的干扰源的注入拉动效应产生的杂散。 频率参考时钟重新定时与RF振荡器时钟同步，用于驱动DRP的整个数字逻辑电路。 这确保了整个系统中不同的时钟沿不会出现相互漂移。 还提出了一种提高ADPLL内数字转换器的分辨率质量的方法。 该方法通过将参考时钟传递通过由Σ-Δ调制器控制的延迟电路来抖动参考时钟。 由于TDC定时估计的不正确的量化，抖动参考时钟降低了对ADPLL输出的相位噪声的影响。

公开(公告)号：US20080057878A1

公开(公告)日：2008-03-06

申请号：US11847008

申请日：2007-08-29

申请人： Robert Staszewski ,  Renaldi Winoto ,  Dirk Leipold

发明人： Robert Staszewski ,  Renaldi Winoto ,  Dirk Leipold

IPC分类号： H04B1/40

CPC分类号： H01L29/7613 ,  B82Y10/00 ,  H01L29/66439 ,  Y10S977/937

摘要： A method of manufacturing a parallel redundant array of single-electron devices. The method includes (a) providing a mask for diffusing a plurality of n-doped regions defined by a first set of a plurality of active regions, (b) providing a mask for disposing a plurality of polysilicon gates defined by a second set of a plurality of exposed regions, wherein an offset between a first member of the plurality of the exposed region of the first set differs in offset from a second member of the plurality of the exposed region of the second set, and (c) fabricating the parallel redundant array of single-electron devices as a function of the offset.

摘要翻译： 一种制造单电子器件的并行冗余阵列的方法。 该方法包括：（a）提供掩模，用于扩散由第一组多个有源区限定的多个n掺杂区，（b）提供掩模，用于设置由第二组 多个暴露区域，其中第一组的多个暴露区域中的第一构件之间的偏移量偏离第二组的多个暴露区域中的第二构件，以及（c）制造并行冗余 作为偏移的函数的单电子器件的阵列。

公开(公告)号：US20080054253A1

公开(公告)日：2008-03-06

申请号：US11846993

申请日：2007-08-29

申请人： Robert Staszewski ,  Renaldi Winoto ,  Dirk Leipold

发明人： Robert Staszewski ,  Renaldi Winoto ,  Dirk Leipold

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L27/092 ,  H01L29/66151 ,  H01L29/88 ,  Y10S438/979 ,  Y10S977/937

摘要： A method of providing a p-type substrate, disposing a pad oxide layer on the p-type substrate, disposing a nitride layer on the pad oxide layer, forming a nitride window in the nitride layer, disposing a field oxide in the nitride window, disposing a polysilicon gate over the field oxide, and diffusing a n-doped region in the p-type substrate, thereby forming at least one single-electron tunnel junction between the polysilicon gate and the n-doped region.

摘要翻译： 一种提供p型衬底的方法，在p型衬底上设置焊盘氧化物层，在衬垫氧化物层上设置氮化物层，在氮化物层中形成氮化物窗，在氮化物窗中设置场氧化物， 在场氧化物上设置多晶硅栅极，并扩散p型衬底中的n掺杂区域，从而在多晶硅栅极和n掺杂区域之间形成至少一个单电子隧道结。