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    Cache directory array recovery mechanism to support special ECC stuck bit matrix
    71.
    发明授权
    Cache directory array recovery mechanism to support special ECC stuck bit matrix 失效
    缓存目录数组恢复机制，支持特殊ECC卡位矩阵

    公开(公告)号：US07272773B2

    公开(公告)日：2007-09-18

    申请号：US10418546

    申请日：2003-04-17

    申请人： Robert Alan Cargnoni ,  Guy Lynn Guthrie ,  Kirk Samuel Livingston ,  William John Starke

    发明人： Robert Alan Cargnoni ,  Guy Lynn Guthrie ,  Kirk Samuel Livingston ,  William John Starke

    IPC分类号： G11C29/00 ,  H03M13/00

    CPC分类号： G06F12/0802 ,  G06F11/1064

    摘要： A method of correcting an error in an ECC protected mechanism of a computer system, such as a cache or system bus, by applying data with a number of bits N to an error correction code (ECC) matrix to yield an error detection syndrome, wherein the ECC matrix has a plurality of rows and columns with a given column corresponding to a respective one of the data bits, and selected bits are set in the ECC matrix along each column and each row such that encoding for the ECC matrix allows N-bit error correction and (N−1)-bit error detection. When an error is detected and after it is corrected, the corrected data is inverted and then rewritten to the cache array. The corresponding inversion bit for this entry is accordingly set to indicate that the data as currently stored is inverted.

    摘要翻译： 一种通过将具有多个位N的数据应用于纠错码（ECC）矩阵来校正诸如高速缓存或系统总线的计算机系统的ECC保护机制中的错误的方法，以产生错误检测综合征，其中 ECC矩阵具有多个行和列，给定列对应于相应的一个数据位，并且所选择的位在每个列和每行的ECC矩阵中被设置，使得对于ECC矩阵的编码允许N位 纠错和（N-1）位错误检测。 当检测到错误并且在其被校正之后，校正的数据被反转，然后被重写到高速缓存阵列。 因此，该条目的相应的反转位被设置为指示当前存储的数据被反转。

    Acceleration of input/output (I/O) communication through improved address translation
    73.
    发明授权
    Acceleration of input/output (I/O) communication through improved address translation 失效
    通过改进地址转换来加速输入/输出（I / O）通信

    公开(公告)号：US06976148B2

    公开(公告)日：2005-12-13

    申请号：US10339766

    申请日：2003-01-09

    申请人： Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Guy Lynn Guthrie ,  William John Starke

    发明人： Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Guy Lynn Guthrie ,  William John Starke

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1027 ,  G06F12/1081

    摘要： An I/O communication adapter receives from a processor core an I/O command referencing an effective address within an effective address space of the processor core that identifies a storage location. In response to receipt of the I/O command, the I/O communication adapter translates the effective address into a real address by reference to a translation data structure. The I/O communication adapter then accesses the storage location utilizing the real address to perform an I/O data transfer specified by the I/O command.

    摘要翻译： I / O通信适配器从处理器核心接收参考在处理器核心的有效地址空间内识别存储位置的有效地址的I / O命令。 响应于I / O命令的接收，I / O通信适配器通过参考翻译数据结构将有效地址转换成实地址。 然后，I / O通信适配器使用实际地址访问存储位置，以执行由I / O命令指定的I / O数据传输。

    High performance multiprocessor system with exclusive-deallocate cache state
    74.
    发明授权
    High performance multiprocessor system with exclusive-deallocate cache state 失效
    具有独占解除缓存状态的高性能多处理器系统

    公开(公告)号：US06385702B1

    公开(公告)日：2002-05-07

    申请号：US09437198

    申请日：1999-11-09

    申请人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

    发明人： Ravi Kumar Arimilli ,  Lakshminarayana Baba Arimilli ,  John Steven Dodson ,  Guy Lynn Guthrie ,  William John Starke

    IPC分类号： G06F1200

    CPC分类号： G06F12/0831 ,  G06F12/0811

    摘要： A cache coherency protocol uses a “Exclusive-Deallocate” (ED) coherency state to indicate that a particular value is currently held in an upper level cache in an exclusive, unmodified form (not shared with any other caches of the computer system, including caches associated with the same processing unit), so that the value can conveniently be modified without any lower level bus transactions since no lower level caches have allocated a line for the value. If the value is subsequently modified in the upper level cache, its coherency state is simply switched to “modified” without the need for any bus transactions. Conversely, if the value is evicted from the upper level cache without ever having been modified, it can be loaded into the lower level cache with a coherency state indicating that the lower level cache contains the unmodified value exclusive of all other caches in other processing units of the computer system. If the value is initially loaded into the upper level cache from a cache of another processing unit, or from a lower level cache of the same processing unit, then the upper level cache may be selectively programmed to mark the cache line with the ED state.

    摘要翻译： 高速缓存一致性协议使用“独占解除分配”（ED）一致性状态来指示特定值当前以独占未修改的形式（不与计算机系统的任何其他高速缓存共享，包括高速缓存）保持在高级缓存中 与相同的处理单元关联），使得该值可以方便地被修改而没有任何较低级别的总线事务，因为没有较低级别的高速缓存已经为该值分配了一行。 如果该值随后在高级缓存中被修改，则其一致性状态被简单地切换到“修改”，而不需要任何总线事务。 相反，如果该值从上级缓存中被逐出而没有被修改，则可以将其加载到具有一致性状态的相关性状态中，该相关性状态指示低级缓存包含其他处理单元中所有其他高速缓存的排他性的未修改值 的计算机系统。 如果该值最初从另一处理单元的高速缓存或相同处理单元的较低级高速缓存加载到高级缓存中，则可以选择性地编程高级缓存以用ED状态标记高速缓存行。

    Information handling system with immediate scheduling of load operations in a dual-bank cache with single dispatch into write/read data flow
    75.
    发明授权
    Information handling system with immediate scheduling of load operations in a dual-bank cache with single dispatch into write/read data flow 有权
    信息处理系统，可以在双行缓存中立即调度负载操作，并单次调度到写入/读取数据流

    公开(公告)号：US08140765B2

    公开(公告)日：2012-03-20

    申请号：US12424228

    申请日：2009-04-15

    申请人： Sanjeev Gai ,  Guy Lynn Guthrie ,  Hugh Shen ,  William John Starke

    发明人： Sanjeev Gai ,  Guy Lynn Guthrie ,  Hugh Shen ,  William John Starke

    IPC分类号： G06F13/28

    CPC分类号： G06F12/0846 ,  G06F12/0897

    摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides a single dispatch point into the data flow to the dual cache banks of the L2 cache memory.

    摘要翻译： 信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。 处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。 处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。 仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。 L2高速缓冲存储器包括双数据库，使得一个存储体可以执行加载操作，而另一个存储体执行存储操作。 缓存系统向数据流提供单个调度点到L2缓存存储器的双缓存组。

    L2 cache controller with slice directory and unified cache structure
    77.
    发明授权
    L2 cache controller with slice directory and unified cache structure 失效
    L2缓存控制器具有片目录和统一缓存结构

    公开(公告)号：US08001330B2

    公开(公告)日：2011-08-16

    申请号：US12325266

    申请日：2008-12-01

    申请人： Leo James Clark ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  William John Starke

    发明人： Leo James Clark ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  William John Starke

    IPC分类号： G06F13/00

    CPC分类号： G06F12/0851 ,  G06F12/0811

    摘要： A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first directory to access the first array slice while using a second directory to access the second array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In one embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. The cache array is arranged with rows and columns of cache sectors wherein a cache line is spread across sectors in different rows and columns, with a portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency.

    摘要翻译： 缓存存储器将具有单个访问/命令端口的高速缓存阵列逻辑地分区成至少两个切片，并且使用第一目录来访问第一阵列片，同时使用第二目录来访问第二阵列片，但是从高速缓存目录 使用控制单个访问/命令端口的单个缓存仲裁器进行管理。 在一个实施例中，每个高速缓存目录具有其自己的目录仲裁器来处理冲突的内部请求，并且目录仲裁器与高速缓存仲裁器通信。 高速缓存阵列布置有高速缓存扇区的行和列，其中高速缓存行分布在不同行和列中的扇区之间，其中一部分给定高速缓存行位于具有第一延迟的第一列中，并且给定的另一部分 高速缓存线位于具有大于第一等待时间的第二等待时间的第二列中。

    INFORMATION HANDLING SYSTEM WITH IMMEDIATE SCHEDULING OF LOAD OPERATIONS
    78.
    发明申请
    INFORMATION HANDLING SYSTEM WITH IMMEDIATE SCHEDULING OF LOAD OPERATIONS 审中-公开
    信息处理系统，立即加载运行

    公开(公告)号：US20100268895A1

    公开(公告)日：2010-10-21

    申请号：US12424284

    申请日：2009-04-15

    申请人： Sanjeev Ghai ,  Guy Lynn Guthrie ,  Stephen Powell ,  William John Starke

    发明人： Sanjeev Ghai ,  Guy Lynn Guthrie ,  Stephen Powell ,  William John Starke

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0855 ,  G06F12/126

    摘要： An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. When the L2 cache memory finishes servicing the interrupting load request, the L2 cache memory may return to servicing the interrupted store request at the point of interruption.

    摘要翻译： 信息处理系统（IHS）包括具有高速缓冲存储器系统的处理器。 处理器包括具有耦合到L2高速缓冲存储器的L1高速缓冲存储器的处理器核心。 处理器包括仲裁机制，其控制对L2高速缓冲存储器的加载和存储请求。 仲裁机制包括控制逻辑，其允许加载请求中断L2高速缓冲存储器当前正在服务的存储请求。 当L2高速缓存存储器完成对中断加载请求的服务时，L2高速缓冲存储器可以在中断点返回服务中断的存储请求。

    Enhanced processor virtualization mechanism via saving and restoring soft processor/system states
    80.
    发明授权
    Enhanced processor virtualization mechanism via saving and restoring soft processor/system states 失效
    通过保存和恢复软处理器/系统状态来增强处理器虚拟化机制

    公开(公告)号：US07493478B2

    公开(公告)日：2009-02-17

    申请号：US10313308

    申请日：2002-12-05

    申请人： Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Guy Lynn Guthrie ,  William John Starke

    发明人： Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Guy Lynn Guthrie ,  William John Starke

    IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

    CPC分类号： G06F9/30123 ,  G06F9/30116 ,  G06F9/3013 ,  G06F9/462

    摘要： A method and system are disclosed for saving soft state information, which is non-critical for executing a process in a processor, upon a receipt of a process interrupt by the processor. The soft state is transmitted to a memory associated with the processor via a memory interface. Preferably, the soft state is transmitted within the processor to the memory interface via a scan-chain pathway within the processor, which allows functional data pathways to remain unobstructed by the storage of the soft state. Thereafter, the stored soft state can be restored from memory when the process is again executed.

    摘要翻译： 公开了一种方法和系统，用于在接收到处理器的处理中断时，保存对于在处理器中执行处理不重要的软​​状态信息。 软状态经由存储器接口传送到与处理器相关联的存储器。 优选地，软状态在处理器内经由处理器内的扫描链路径在处理器内传送到存储器接口，这允许功能数据路径通过软状态的存储而保持不受阻碍。 此后，当再次执行处理时，可以从存储器恢复存储的软状态。