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71.发明授权Three input arithmetic logic unit with controllable shifter and mask generator 失效三输入算术逻辑单元，带可控制移位器和掩码发生器
公开(公告)号：US5634065A
公开(公告)日：1997-05-27
申请号：US475134
申请日：1995-06-07
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
摘要： A three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default barrel rotate amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register.
摘要翻译： 三输入算术逻辑单元（230），其生成由功能信号选择的三个输入的组合。 第二输入信号来自可控筒旋转器（235）。 旋转量是存储在特殊数据寄存器中的默认旋转量，从数据寄存器或零调用的预定数据位组。 恒定源（236）连接到筒旋转器（235）以提供“1”的多位数字信号。 这允许产生形式2N的第二输入信号，其中N是旋转量。 桶旋转器（235）的输出可以独立于算术逻辑单元（230）的结果存储。 第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。 掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。 该掩模输入信号可以是由多路复用器选择的默认桶旋转量或第三输入信号的预定数量的最低有效位。 选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。
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公开(公告)号：US5608468A
公开(公告)日：1997-03-04
申请号：US482477
申请日：1995-06-07
CPC分类号： H04N7/0122 , H04N5/7458
摘要： A spatial light modulator with hexagonal elements or pixels. The elements include a reflective hexagonal surface supported by flexible hinges. The hinges are in turn supported by support posts away from a substrate. On the substrate are control or address electrodes which control the direction of deflection of the reflective surface by selective build up of electrostatic forces. The use of hexagonal pixels allow the posts and electrodes to be arrayed in horizontal lines, thereby allowing reset of horizontal lines of the pixels.
摘要翻译： 具有六边形元素或像素的空间光调制器。 元件包括由柔性铰链支撑的反射六边形表面。 铰链又由远离基底的支撑柱支撑。 在基板上是通过选择性地建立静电力来控制反射表面的偏转方向的控制或寻址电极。 使用六边形像素允许柱和电极以水平线排列，从而允许像素的水平线的复位。
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公开(公告)号：US5600847A
公开(公告)日：1997-02-04
申请号：US475162
申请日：1995-06-07
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
CPC分类号： G06F7/57
摘要： A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. A controllable shifter is an alternative to the barrel rotator (235). The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default barrel rotate amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.
摘要翻译： 数据处理装置包括产生由功能信号选择的三个输入的组合的三输入算术逻辑单元（230）。 数据寄存器（200）存储三个数据输入和算术逻辑单元输出。 第二输入信号来自可控筒旋转器（235）。 旋转量是存储在特殊数据寄存器中的默认旋转量，从数据寄存器或零调用的预定数据位组。 恒定源（236）连接到筒旋转器（235）以提供“1”的多位数字信号。 这允许产生形式2N的第二输入信号，其中N是旋转量。 桶旋转器（235）的输出可以独立于算术逻辑单元（230）的结果存储。 可控制的换档器是桶旋转器（235）的替代品。 第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。 掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。 该掩模输入信号可以是由多路复用器选择的默认桶旋转量或第三输入信号的预定数量的最低有效位。 选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。 在本发明的优选实施例中，三输入算术逻辑单元（230）被实现为作为在图像处理中使用的多处理器集成电路（100）的一部分的数据处理器电路。
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74.发明授权Multiple operations employing divided arithmetic logic unit and multiple flags register 失效多个操作采用分割算术逻辑单元和多个标志寄存器
公开(公告)号：US5592405A
公开(公告)日：1997-01-07
申请号：US484579
申请日：1995-06-07
IPC分类号： G06F15/167 , G06F12/02 , G06F12/06 , G06F15/173 , G06F15/80 , G06F7/38 , G06F7/00 , G06F7/50
CPC分类号： G06F15/17375 , G06F12/0284
摘要： A data processing apparatus includes an arithmetic logic unit is divided into a plurality of sections. Each section generates at a corresponding output a digital resultant signal representing a combination of respective subsets of first and second multibit digital inputs. The arithmetic logic unit includes a status detector generating a single bit status signal indicative of said digital resultant signal of a corresponding section of the arithmetic logic unit. These single bit status signals are stored in predetermined locations within a multiple flags register. An options register stores an indication of the number of sections selected from a plurality of possible number of sections into which the arithmetic logic unit is divided. The arithmetic logic unit is further connected to the multiple flags register so that each section selects for output either corresponding bits of the first multibit digital input or the second multibit digital input dependent upon the digital state of a corresponding single status bit in the multiple flags register. This technique permits a variety of functions such as add with saturation, maximum, pixel transparency and color expansion.
摘要翻译： 一种数据处理装置，包括被分成多个部分的算术逻辑单元。 每个部分在相应的输出处产生表示第一和第二多位数字输入的各个子集的组合的数字结果信号。 算术逻辑单元包括状态检测器，其产生指示算术逻辑单元的相应部分的所述数字结果信号的单位状态信号。 这些单位状态信号存储在多标志寄存器内的预定位置。 选项寄存器存储从算术逻辑单元划分到的多个可能数量的区段中选择的区段数量的指示。 算术逻辑单元还连接到多标志寄存器，使得每个部分选择输出第一多位数字输入或第二多位数字输入的对应位，取决于多标志寄存器中对应的单个状态位的数字状态 。 这种技术允许各种功能，如饱和度，最大值，像素透明度和颜色扩展等。
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公开(公告)号：US5592231A
公开(公告)日：1997-01-07
申请号：US477743
申请日：1995-06-07
CPC分类号： H04N7/012
摘要： A method for processing video data to produce a progressively scanned signal from an input of conventional interlaced video. The data is received at a processor (1), used to determine a motion signal (26) over time between field of the data. The motion signal is filtered to reduce errors caused by noise-corrupted video sources and then further filtered to spread out the determined motion signal. Edge information (30) is located and combined with the motion signal to produce an integrated progressive-scan signal (36) for display on a video display device, producing images with sharper edges and motion signals which have a lower susceptibility to noise.
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公开(公告)号：US5590350A
公开(公告)日：1996-12-31
申请号：US159282
申请日：1993-11-30
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
CPC分类号： G06F7/57
摘要： A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. A controllable shifter is an alternative to the barrel rotator (235). The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default barrel rotate amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.
摘要翻译： 数据处理装置包括产生由功能信号选择的三个输入的组合的三输入算术逻辑单元（230）。 数据寄存器（200）存储三个数据输入和算术逻辑单元输出。 第二输入信号来自可控筒旋转器（235）。 旋转量是存储在特殊数据寄存器中的默认旋转量，从数据寄存器或零调用的预定数据位组。 恒定源（236）连接到筒旋转器（235）以提供“1”的多位数字信号。 这允许产生形式2N的第二输入信号，其中N是旋转量。 桶旋转器（235）的输出可以独立于算术逻辑单元（230）的结果存储。 可控制的换档器是桶旋转器（235）的替代品。 第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。 掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。 该掩模输入信号可以是由多路复用器选择的默认桶旋转量或第三输入信号的预定数量的最低有效位。 选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。 在本发明的优选实施例中，三输入算术逻辑单元（230）被实现为作为在图像处理中使用的多处理器集成电路（100）的一部分的数据处理器电路。
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公开(公告)号：US5508750A
公开(公告)日：1996-04-16
申请号：US383349
申请日：1995-02-03
申请人： Gregory J. Hewlett , Robert J. Gove
发明人： Gregory J. Hewlett , Robert J. Gove
CPC分类号： H04N5/147 , G11B27/031 , H04N19/142 , H04N19/179 , H04N19/46 , H04N19/85 , H04N19/87 , H04N5/7458 , H04N7/0112 , H04N7/012
摘要： A method of encoding video display data, after that data has been previously converted from a film frame rate to a faster video frame rate, such as by 3:2 pulldown. The data is first re-converted to the film frame format, as progressive frames (21). This progressive frame data is processed to determine where scene cuts occur (22). The data is then encoded consistent with MPEG encoding techniques, but with the scene cut information being used to begin groups of pictures (GOPs) at scene cuts and to determine where intrapictures, predicted pictures, or interpolated pictures shall occur (23).
摘要翻译： 一种编码视频显示数据的方法，之后数据已经预先从电影帧速率转换为更快的视频帧率，例如通过3：2下拉。 数据首先被重新转换为电影帧格式，作为渐进帧（21）。 处理该渐进帧数据以确定场景切割发生的位置（22）。 然后将数据与MPEG编码技术一致地编码，但是场景切割信息用于在场景切割时开始图像组（GOP），并确定图像内部，预测图像或内插图像应发生的位置（23）。
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公开(公告)号：US5499060A
公开(公告)日：1996-03-12
申请号：US177013
申请日：1994-01-04
CPC分类号： H04N9/646
摘要： A system (14') for processing pixel video data having a selectable number of bits is provided. The system (14') comprises first, second and third video processors (20), (22) and (24). The first video processor (20) receives and processes pixel data of a luminance video signal. The second video processor (22) may receive and process pixel data of a chrominance video signal and may generate one of first, second and third video signal outputs. The third video processor (24) may process the chrominance video signal and may also generate at least two of the output video signals.
摘要翻译： 提供了一种用于处理具有可选位数的像素视频数据的系统（14'）。 系统（14'）包括第一，第二和第三视频处理器（20），（22）和（24）。 第一视频处理器（20）接收并处理亮度视频信号的像素数据。 第二视频处理器（22）可以接收和处理色度视频信号的像素数据，并且可以产生第一，第二和第三视频信号输出中的一个。 第三视频处理器（24）可以处理色度视频信号，并且还可以产生至少两个输出视频信号。
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公开(公告)号：US5489952A
公开(公告)日：1996-02-06
申请号：US91852
申请日：1993-07-14
CPC分类号： H04N7/0122 , H04N5/7458
摘要： A multi-format display system including hardware and algorithms for digital and High Definition Television. The system includes a light source (120), a tuner/preprocessor unit (114), a processor unit (116), a spatial light modulator (118), and a display surface (128). The processor unit can scale and format the data for a number of standardized-format video broadcast signals, and can perform additional interpolation to eliminate artifacts.
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80.发明授权Plural memory access address generation employing guide table entries forming linked list 失效使用指导表条目形成链表的多个存储器访问地址生成
公开(公告)号：US5487146A
公开(公告)日：1996-01-23
申请号：US209124
申请日：1994-03-08
摘要： A data processing device includes a memory, a control circuit, a guide table and an address generating circuit. The control circuit receives a packet transfer request and packet transfer parameters. The packet transfer parameters include a start address, dimension values defining a block of addresses, guide table having guide table entries and a table pointer. Each guide table entry has an address value. The table pointer initially points to a first guide table entry in the guide table. The address generating circuit forms a set of a block of addresses for memory access corresponding to each guide table entry, having a start address from a predetermined combination of the start address and the address value of the guide table entry. The block of addresses are formed from the dimension values. Following the memory accesses, the address generating circuit updates the table pointer to point to a next entry in the guide table. The address generating circuit may add the address value to the prior block starting address or add the guide table value to the starting address. The memory access may be a memory read from the block of addresses or a memory write to the block of addresses.
摘要翻译： 数据处理装置包括存储器，控制电路，引导表和地址产生电路。 控制电路接收分组传送请求和分组传送参数。 分组传送参数包括起始地址，定义地址块的维度值，具有指导表条目的指南表和表指针。 每个指南表项具有地址值。 表指针最初指向指南表中的第一个指南表项。 地址生成电路形成与每个指导表条目对应的用于存储器访问的地址块的集合，具有来自引导表条目的起始地址和地址值的预定组合的起始地址。 地址块由维度值形成。 在存储器访问之后，地址产生电路更新表指针以指向指南表中的下一条目。 地址产生电路可以将地址值添加到先前块开始地址，或者将引导表值添加到起始地址。 存储器访问可以是从地址块读取的存储器或写入地址块的存储器。
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