公开(公告)号：US20200176493A1

公开(公告)日：2020-06-04

申请号：US16615156

申请日：2018-05-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takayuki IKEDA ,  Yoshiyuki KUROKAWA ,  Shintaro HARADA ,  Hidetomo KOBAYASHI ,  Roh YAMAMOTO ,  Kiyotaka KIMURA ,  Takashi NAKAGAWA ,  Yusuke NEGORO

IPC: H01L27/146 ,  H04N5/341 ,  H04N5/374 ,  H01L29/786 ,  H04N5/3745 ,  H01L27/12

Abstract: An imaging device capable of image processing is provided.The imaging device can retain analog data (image data) obtained by an image-capturing operation in a pixel and perform a product-sum operation of the analog data and a predetermined weight coefficient in the pixel to convert the data into binary data. When the binary data is taken in a neural network or the like, processing such as image recognition can be performed. Since enormous volumes of image data can be retained in pixels in the state of analog data, processing can be performed efficiently.

公开(公告)号：US20180026218A1

公开(公告)日：2018-01-25

申请号：US15651192

申请日：2017-07-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidetomo KOBAYASHI ,  Kouhei TOYOTAKA

IPC: H01L51/50 ,  H01L51/05

Abstract: A display device that can be easily and more flexibly designed is provided. The display device includes a pixel circuit and a driver circuit in a display portion. The driver circuit includes a plurality of pulse output circuits. Each of the plurality of pulse output circuits has a function of driving a gate line. The pixel circuit is electrically connected to the gate line. Each of the plurality of pulse output circuits includes a first transistor. The pixel circuit includes a second transistor. A layer including the second transistor is over a layer including the first transistor, and the first transistor and the second transistor overlap with each other.

公开(公告)号：US20180012535A1

公开(公告)日：2018-01-11

申请号：US15641502

申请日：2017-07-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidetomo KOBAYASHI

IPC: G09G3/20 ,  G09G3/36 ,  G06F3/041

CPC classification number: G09G3/2092 ,  G06F3/041 ,  G06F2203/0339 ,  G06F2203/04102 ,  G09G3/2007 ,  G09G3/3225 ,  G09G3/3607 ,  G09G3/3648 ,  G09G3/3688 ,  G09G2300/0456 ,  G09G2300/046 ,  G09G2310/0291 ,  G09G2310/08 ,  G09G2330/021 ,  G09G2360/144

Abstract: The display device includes a pixel and a driver circuit. The driver circuit includes a receiving circuit, a controller, a switching control circuit, and a signal generation circuit. The receiving circuit outputs image data obtained by converting differential signals into parallel data to the controller. The receiving circuit includes a plurality of circuits each including a first amplifier and a second amplifier. The first amplifier and the second amplifier each include a switch and a first transistor for supplying a bias current. The switch has a function of controlling electrical continuity between a wiring for supplying a bias voltage and a gate of the first transistor. The switching control circuit has a function of outputting a switching signal for controlling electrical continuity of the switch.

公开(公告)号：US20170221429A1

公开(公告)日：2017-08-03

申请号：US15409834

申请日：2017-01-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidetomo KOBAYASHI ,  Roh YAMAMOTO ,  Kei TAKAHASHI

IPC: G09G3/36 ,  H01L27/12 ,  H01L29/786 ,  H01L29/66 ,  H05K5/00 ,  G11C27/02

CPC classification number: G09G3/36 ,  G09G3/3688 ,  G09G2310/0291 ,  G09G2310/0294 ,  G11C27/024 ,  H01L27/1225 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: Objects are to provide a semiconductor device with a novel structure, to provide a semiconductor device with low power consumption, and to provide a semiconductor device with a small chip area. A digital-analog converter and a frame memory are included. The frame memory includes a sample-and-hold circuit, a correction circuit, and a source follower circuit. The sample-and-hold circuit retains the analog voltage output from the digital-analog converter. The correction circuit corrects the analog voltage retained in the sample-and-hold circuit. The source-follower circuit outputs the corrected analog voltage. The sample-and-hold-circuit, the correction circuit, and the source follower circuit each comprise a first transistor. The first transistor comprises an oxide semiconductor layer in a semiconductor layer.

公开(公告)号：US20160225773A1

公开(公告)日：2016-08-04

申请号：US15092698

申请日：2016-04-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidetomo KOBAYASHI

IPC: H01L27/105 ,  H01L29/786 ,  H01L29/24 ,  H01L27/12

CPC classification number: H01L27/1052 ,  H01L27/108 ,  H01L27/10805 ,  H01L27/115 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/1255 ,  H01L29/24 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device capable of retaining data for a long time is provided. The semiconductor device includes first to third transistors, a fourth transistor including first and second gates, first to third nodes, a capacitor, and an input terminal. A source of the first transistor is connected to the input terminal. A drain of the first transistor and a source of the second transistor are connected to the first node. A gate of the second transistor, a drain of the second transistor, and a source of the third transistor are connected to the second node. A gate of the third transistor, a drain of the third transistor, the capacitor, and the second gate of the fourth transistor are connected to the third node.

Abstract translation: 提供能够长时间保留数据的半导体器件。 半导体器件包括第一至第三晶体管，包括第一和第二栅极，第一至第三晶体管，电容器和输入端子的第四晶体管。 第一晶体管的源极连接到输入端子。 第一晶体管的漏极和第二晶体管的源极连接到第一节点。 第二晶体管的栅极，第二晶体管的漏极和第三晶体管的源极连接到第二晶体管。 第三晶体管的栅极，第三晶体管的漏极，第四晶体管的电容器和第二栅极连接到第三晶体管。

公开(公告)号：US20160054362A1

公开(公告)日：2016-02-25

申请号：US14830817

申请日：2015-08-20

Applicant: Semiconductor Energy Laboratory Co., LTD.

Inventor： Masashi TSUBUKU ,  Shunpei YAMAZAKI ,  Hidetomo KOBAYASHI ,  Kazuaki OHSHIMA ,  Masashi FUJITA ,  Toshihiko TAKEUCHI

IPC: G01R19/25 ,  H01L27/06 ,  H01L29/24 ,  H01L29/786

CPC classification number: H01L29/24 ,  G01R19/0092 ,  G01R31/2608 ,  G01R31/2621 ,  H01L22/14 ,  H01L27/0629 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A current measurement method with which an extremely low current can be measured is provided. In the method, a charge written to a first terminal of a capacitor through a transistor under test is retained, data on the correspondence between a potential V of the first terminal of the capacitor and Time t is generated, and a stretched exponential function represented by Formula (a1) is fitted to the data to determine parameters of Formula (a1). The derivative of Formula (a1) with respect to time gives a stretched exponential function describing an off-state current of the transistor under test. The potential of the first terminal of the capacitor is measured using an on-state current of a transistor whose gate is connected to the first terminal of the capacitor. V FN  ( t ) = α ×  - ( t τ ) β ( a   1 )

Abstract translation: 提供了可以测量极低电流的电流测量方法。 在该方法中，保持通过被测晶体管向电容器的第一端子写入的电荷，产生电容器的第一端子的电位V与时间t之间的对应关系的数据，以及由 公式（a1）拟合到数据中以确定公式（a1）的参数。 式（a1）相对于时间的导数给出描述被测晶体管截止电流的拉伸指数函数。 使用其栅极连接到电容器的第一端子的晶体管的导通状态电流来测量电容器的第一端子的电位。 V FN（t）=α× - （tτ）＆bgr; （一个1）