公开(公告)号：US20170178728A1

公开(公告)日：2017-06-22

申请号：US15450147

申请日：2017-03-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masashi TSUBUKU ,  Masashi FUJITA

IPC: G11C14/00 ,  G11C13/00

CPC classification number: G11C14/0045 ,  G11C11/401 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/79

Abstract: Provided is a highly reliable semiconductor device, a semiconductor device with a reduced circuit area, a memory element having favorable characteristics, a highly reliable memory element, or a memory element with increased storage capacity per unit volume. A semiconductor device includes a capacitor and a switching element. The capacitor includes a first electrode, a second electrode, and a dielectric. The dielectric is positioned between the first electrode and the second electrode. The switching element includes a first terminal and a second terminal. The first terminal is electrically connected to the first electrode. The following steps are sequentially performed: a first step of turning on the switching element in a first period, a second step of turning off the switching element in a second period, and a third step of turning on the switching element in a third period.

公开(公告)号：US20160217830A1

公开(公告)日：2016-07-28

申请号：US14996635

申请日：2016-01-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masashi TSUBUKU ,  Masashi FUJITA

IPC: G11C5/10

CPC classification number: G11C14/0045 ,  G11C11/401 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/79

Abstract: Provided is a highly reliable semiconductor device, a semiconductor device with a reduced circuit area, a memory element having favorable characteristics, a highly reliable memory element, or a memory element with increased storage capacity per unit volume. A semiconductor device includes a capacitor and a switching element. The capacitor includes a first electrode, a second electrode, and a dielectric. The dielectric is positioned between the first electrode and the second electrode. The switching element includes a first terminal and a second terminal. The first terminal is electrically connected to the first electrode. The following steps are sequentially performed: a first step of turning on the switching element in a first period, a second step of turning off the switching element in a second period, and a third step of turning on the switching element in a third period.

Abstract translation: 提供了一种高度可靠的半导体器件，具有减小的电路面积的半导体器件，具有有利特性的存储元件，高度可靠的存储元件或具有每单位体积的存储容量增加的存储元件。 半导体器件包括电容器和开关元件。 电容器包括第一电极，第二电极和电介质。 电介质位于第一电极和第二电极之间。 开关元件包括第一端子和第二端子。 第一端子电连接到第一电极。 顺序执行以下步骤：在第一周期中接通开关元件的第一步骤，在第二时段中断开开关元件的第二步骤，以及在第三时间段内接通开关元件的第三步骤。

公开(公告)号：US20150129873A1

公开(公告)日：2015-05-14

申请号：US14598384

申请日：2015-01-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Masashi FUJITA ,  Yutaka SHIONOIRI ,  Hiroyuki TOMATSU ,  Hidetomo KOBAYASHI

IPC: H01L27/12 ,  H01L27/108 ,  H01L27/088

CPC classification number: H01L27/1225 ,  H01L21/84 ,  H01L27/088 ,  H01L27/108 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1222 ,  H01L27/1251

Abstract: A first field-effect transistor provided over a substrate in which an insulating region is provided over a first semiconductor region and a second semiconductor region is provided over the insulating region; an insulating layer provided over the substrate; a second field-effect transistor that is provided one flat surface of the insulating layer and includes an oxide semiconductor layer; and a control terminal are provided. The control terminal is formed in the same step as a source and a drain of the second field-effect transistor, and a voltage for controlling a threshold voltage of the first field-effect transistor is supplied to the control terminal.

Abstract translation: 提供在绝缘区域上方设置有在第一半导体区域和第二半导体区域上设置绝缘区域的衬底上的第一场效应晶体管; 设置在所述基板上的绝缘层; 第二场效应晶体管，其设置在所述绝缘层的一个平面上，并且包括氧化物半导体层; 并提供控制终端。 控制端子以与第二场效应晶体管的源极和漏极相同的步骤形成，并且用于控制第一场效应晶体管的阈值电压的电压被提供给控制端子。

公开(公告)号：US20200168710A1

公开(公告)日：2020-05-28

申请号：US16775394

申请日：2020-01-29

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Masashi TSUBUKU ,  Shunpei YAMAZAKI ,  Hidetomo KOBAYASHI ,  Kazuaki OHSHIMA ,  Masashi FUJITA ,  Toshihiko TAKEUCHI

IPC: H01L29/24 ,  H01L27/12 ,  H01L29/786 ,  G01R19/00 ,  H01L21/66

Abstract: A semiconductor device in which a transistor has the characteristic of low off-state current is provided. The transistor comprises an oxide semiconductor layer having a channel region whose channel width is smaller than 70 nm. A temporal change in off-state current of the transistor over time can be represented by Formula (a2). In Formula (a2), IOFF represents the off-state current, t represents time during which the transistor is off, α and τ are constants, β is a constant that satisfies 0

公开(公告)号：US20170272079A1

公开(公告)日：2017-09-21

申请号：US15610705

申请日：2017-06-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masashi FUJITA ,  Yutaka SHIONOIRI ,  Kiyoshi KATO ,  Hidetomo KOBAYASHI

IPC: H03K19/177 ,  H03K19/173

Abstract: An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.

公开(公告)号：US20250029648A1

公开(公告)日：2025-01-23

申请号：US18715300

申请日：2022-12-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Masashi FUJITA ,  Kazuaki OHSHIMA

IPC: G11C11/405 ,  H10B12/00

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a register. The register includes a flip-flop and a plurality of data retention circuits. The flip-flop includes a first transistor in which a semiconductor layer including a channel formation region is silicon, an input terminal of the flip-flop is electrically connected to each of output terminals of the data retention circuits, and an output terminal of the flip-flop is electrically connected to each of input terminals of the data retention circuits. The data retention circuits include a second transistor in which a semiconductor layer including a channel formation region is an oxide semiconductor, and when the second transistor is in a non-conduction state, the data retention circuits have a function of retaining a potential corresponding to data corresponding to a plurality of tasks. A state control portion rewrites data that the flip-flop has on the basis of data retained in the data retention circuits in accordance with the plurality of tasks executed by a processor core.

公开(公告)号：US20210135674A1

公开(公告)日：2021-05-06

申请号：US17150859

申请日：2021-01-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masashi FUJITA ,  Yutaka SHIONOIRI ,  Kiyoshi KATO ,  Hidetomo KOBAYASHI

IPC: H03K19/17728 ,  H03K19/173 ,  H03K19/17772 ,  H03K19/17758

Abstract: An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.

公开(公告)号：US20170338349A1

公开(公告)日：2017-11-23

申请号：US15585849

申请日：2017-05-03

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Masashi TSUBUKU ,  Kazuaki OHSHIMA ,  Masashi FUJITA ,  Daigo SHIMADA ,  Tsutomu MURAKAWA

IPC: H01L29/786 ,  G11C11/401 ,  H01L27/12 ,  H01L27/1156

CPC classification number: H01L29/7869 ,  G11C11/401 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/78621 ,  H01L29/78648 ,  H01L29/78696

Abstract: A semiconductor device that can measure a minute current. The semiconductor device includes a first transistor, a second transistor, a node, and a capacitor. The first transistor includes an oxide semiconductor in a channel formation region. The node is electrically connected to a gate of the second transistor and a first terminal of the capacitor. The node is brought into an electrically floating state by turning off the first transistor after a potential V0 is supplied. Change in a potential VFN of the node over time is expressed by Formula (1). In Formula (1), t is elapsed time after the node is brought into the electrically floating state, τ is a constant with a unit of time, and β is a constant greater than or equal to 0.4 and less than or equal to 0.6. V FN  ( t ) = V 0 × e - ( t τ ) β ( 1 )

公开(公告)号：US20160054362A1

公开(公告)日：2016-02-25

申请号：US14830817

申请日：2015-08-20

Applicant: Semiconductor Energy Laboratory Co., LTD.

Inventor： Masashi TSUBUKU ,  Shunpei YAMAZAKI ,  Hidetomo KOBAYASHI ,  Kazuaki OHSHIMA ,  Masashi FUJITA ,  Toshihiko TAKEUCHI

IPC: G01R19/25 ,  H01L27/06 ,  H01L29/24 ,  H01L29/786

CPC classification number: H01L29/24 ,  G01R19/0092 ,  G01R31/2608 ,  G01R31/2621 ,  H01L22/14 ,  H01L27/0629 ,  H01L27/1225 ,  H01L27/1255 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A current measurement method with which an extremely low current can be measured is provided. In the method, a charge written to a first terminal of a capacitor through a transistor under test is retained, data on the correspondence between a potential V of the first terminal of the capacitor and Time t is generated, and a stretched exponential function represented by Formula (a1) is fitted to the data to determine parameters of Formula (a1). The derivative of Formula (a1) with respect to time gives a stretched exponential function describing an off-state current of the transistor under test. The potential of the first terminal of the capacitor is measured using an on-state current of a transistor whose gate is connected to the first terminal of the capacitor. V FN  ( t ) = α ×  - ( t τ ) β ( a   1 )

Abstract translation: 提供了可以测量极低电流的电流测量方法。 在该方法中，保持通过被测晶体管向电容器的第一端子写入的电荷，产生电容器的第一端子的电位V与时间t之间的对应关系的数据，以及由 公式（a1）拟合到数据中以确定公式（a1）的参数。 式（a1）相对于时间的导数给出描述被测晶体管截止电流的拉伸指数函数。 使用其栅极连接到电容器的第一端子的晶体管的导通状态电流来测量电容器的第一端子的电位。 V FN（t）=α× - （tτ）＆bgr; （一个1）

公开(公告)号：US20240411134A1

公开(公告)日：2024-12-12

申请号：US18698873

申请日：2022-10-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Masashi FUJITA ,  Yoshiyuki KUROKAWA ,  Hiromichi GODO ,  Seiko INOUE ,  Kazuma FURUTANI ,  Kouhei TOYOTAKA

IPC: G02B27/01 ,  G02B27/00 ,  H04N13/344 ,  H04N13/383

Abstract: An optical device of the present invention includes a display apparatus (10) and an optical system (12). The display apparatus (10) includes a display region (60) and a sensor region (52). The optical system (12) includes a first mirror (21) and a second mirror (22). The first mirror (21) includes a first surface and a second surface. The display region (60) has a function of emitting first light (31). The first mirror (21) is provided on an optical path of the first light (31) and has a function of transmitting the first light (31) incident on the first surface to the second surface and a function of reflecting second light (33) incident on the second surface. The second mirror (22) is provided on an optical path of the second light (33) and has a function of reflecting the second light (33). The sensor region (52) has a function of detecting the second light (33) via the first mirror (21) and the second mirror (22).