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71.发明授权Method and system for case-splitting on nodes in a symbolic simulation framework 有权符号仿真框架中节点分割的方法和系统公开(公告)号：US07363603B2
公开(公告)日：2008-04-22
申请号：US11225651
申请日：2005-09-13
CPC分类号： G06F17/504
摘要： A method for performing verification includes receiving a design and building for the design an intermediate binary decision diagram set containing one or more nodes representing one or more variables. A first case-splitting is performed upon a first fattest variable from among the one or more variables represented by the one or more nodes by setting the first fattest variable to a primary value, and a first cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using an inverse of the primary value to generate a first cofactored binary decision diagram set. A second cofactoring is performed upon the intermediate binary decision diagram set with respect to the one or more nodes using the primary value to generate a second cofactored binary decision diagram set, and verification of the design is performed by evaluating a property of the second cofactored binary decision diagram set.
摘要翻译： 用于执行验证的方法包括：为设计接收设计和构建包含表示一个或多个变量的一个或多个节点的中间二进制判定图集。 通过将第一个胖子变量设置为一个初始值，对由一个或多个节点表示的一个或多个变量中的第一个胖子变量执行第一个分解，并且对该中间二进制判定图集执行第一个共同构想 相对于使用主值的逆的一个或多个节点来生成第一辅因子二进制决策图集。 对相对于一个或多个节点设置的中间二进制判定图，使用主值来生成第二共有二元决策图集，执行第二共同构想，并且通过评估第二构成二进制的属性来执行设计的验证 决策图集。
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72.发明授权Method and system for building binary decision diagrams efficiently in a structural network representation of a digital circuit 有权在数字电路的结构网络表示中有效构建二进制决策图的方法和系统公开(公告)号：US07340473B2
公开(公告)日：2008-03-04
申请号：US10926587
申请日：2004-08-26
IPC分类号： G06F17/50
CPC分类号： G06F17/30958 , G06F17/504 , Y10S707/99942
摘要： A method, system and computer program product for building decision diagrams efficiently in a structural network representation of a digital circuit using a dynamic resource constrained and interleaved depth-first-search and modified breadth-first-search schedule is disclosed. The method includes setting a first size limit for a first set of one or more m-ary decision representations describing a logic function and setting a second size limit for a second set of one or more m-ary decision representations describing a logic function. The first set of m-ary decision representations of the logic function is then built with one of the set of a depth-first technique or a breadth-first technique until the first size limit is reached, and a second set of m-ary decision representations of the logic function is built with the other technique until the second size limit is reached. In response to determining that a union of first set and the second set of m-ary decision representations do not describe the logic function, the first and second size limits are increased, and the steps of building the first and second set are repeated. In response to determining that the union of the first set of m-ary decision representations and the second set of m-ary decision representations describe the logic function, the union is reported.
摘要翻译： 公开了一种用于在使用动态资源约束和交织的深度优先搜索和修改的宽度优先搜索时间表的数字电路的结构网络表示中有效地构建决策图的方法，系统和计算机程序产品。 该方法包括：对描述逻辑功能的一个或多个多元决策表示的第一集合设置第一大小限制，并为描述逻辑功能的一个或多个虚拟决策表示的第二组设置第二大小限制。 然后，利用深度优先技术或宽度优先技术的集合之一构建逻辑功能的第一组m元决定表示，直到达到第一大小限制，并且第二组m元决定 使用其他技术构建逻辑功能的表示，直到达到第二个大小限制。 响应于确定第一集合和第二组m元决定表示的并集不描述逻辑函数，增加第一和第二大小限制，并且重复构建第一集合和第二集合的步骤。 响应于确定第一组m元决策表示和第二组m元决策表示的并集描述逻辑函数，报告联合。
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73.发明申请Method and Processor for Performing a Floating-Point Instruction Within a Processor 审中-公开在处理器内执行浮点指令的方法和处理器公开(公告)号：US20070038693A1
公开(公告)日：2007-02-15
申请号：US11462069
申请日：2006-08-03
IPC分类号： G06F7/38
CPC分类号： G06F7/49936
摘要： The invention relates to a method for performing floating-point instructions within a processor of a data processing system is described, wherein an input of said floating-point instruction comprises a normal or a denormal floating-point number. Said method comprises the steps of storing said floating-point number, normalization of said floating-point number by counting the leading zeros of the mantissa, shifting the fraction part to the left by the number of leading zeros and simultaneously decrementing the exponent by one for every position that the fraction part is shifted to the left, wherein it the input is a normal floating point number the normalization is done after counting no leading zero of the mantissa, execution of a floating point instruction, wherein said normalized floating-point number is utilized as input for the floating point instruction, and storing of a floating-point result. Furthermore a processor to be used to perform said method is described.
摘要翻译： 本发明涉及一种用于在数据处理系统的处理器内执行浮点指令的方法，其中所述浮点指令的输入包括正常或非正常浮点数。 所述方法包括以下步骤：存储所述浮点数，通过对尾数的前导零进行计数来归一化所述浮点数，将分数部分向左移动前导零的数量，同时将指数递减1， 分数部分向左移动的每个位置，其中输入是普通浮点数，在不计算尾数的前导零之后进行归一化，执行浮点指令，其中所述标准化浮点数为 用作浮点指令的输入，以及浮点结果的存储。 此外，描述了用于执行所述方法的处理器。
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公开(公告)号：US20070011633A1
公开(公告)日：2007-01-11
申请号：US11385928
申请日：2006-03-21
申请人： Kai Weber , Christian Jacobi , Nico Gulden , Viresh Paruthi , Klaus Keuerleber
发明人： Kai Weber , Christian Jacobi , Nico Gulden , Viresh Paruthi , Klaus Keuerleber
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： A method, a computer program product and a system for performing functional verification logic circuits. The invention enables the functional formal verification of a hardware logic design by replacing the parts that cannot be formally verified easily. In one form the invention is applied to a logic design including a multiplier circuit. The multiplier is replaced (51) by pseudo inputs. The input signal values of the multiplier circuit are determined (54) automatically from a counterexample (53) delivered (52) by a functional formal verification system for a modified design where the multiplier is replaced by pseudo signals. The input signal values are combined (55) with other known inputs to form a test case (56) file that can be used by a logic simulator to analyse the counterexample (52) on the unmodified hardware design including the multiplier.
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公开(公告)号：US20060012399A1
公开(公告)日：2006-01-19
申请号：US10891771
申请日：2004-07-15
申请人： Sang Dhong , Christian Jacobi , Hwa-Joon Oh , Silvia Mueller
发明人： Sang Dhong , Christian Jacobi , Hwa-Joon Oh , Silvia Mueller
IPC分类号： H03K19/094
CPC分类号： H03K17/223 , H03K17/005
摘要： A method, a computer program, and an apparatus are provided to protect transmission gates in a multiplexer (mux). Because transmission gates are much faster than the more convention AND-OR arrays, transmission gate usage in muxes are being used more often in high speed circuitry. However, transmission gate have a significant problem in that short circuit are possible for situations where there is not a one-hot select signal. Therefore, to eliminate the problem, logic gates are utilized specifically during Power-On Reset (POR) to force a one-hot selection to prevent any possible short circuits.
摘要翻译： 提供了一种方法，计算机程序和装置来保护复用器（多路复用器）中的传输门。 因为传输门比更常规的AND-OR阵列快得多，所以在高速电路中更频繁地使用多路复用器中的传输门使用。 然而，传输门具有显着的问题，即在没有单热选择信号的情况下短路是可能的。 因此，为了消除这个问题，在上电复位（POR）期间特别使用逻辑门来强制单热选择以防止任何可能的短路。
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公开(公告)号：US09361115B2
公开(公告)日：2016-06-07
申请号：US13524882
申请日：2012-06-15
CPC分类号： G06F9/3861 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/3863 , G06F9/462 , G06F9/466 , G06F9/467
摘要： A TRANSACTION BEGIN instruction begins execution of a transaction and includes a general register save mask having bits, that when set, indicate registers to be saved in the event the transaction is aborted. At the beginning of the transaction, contents of the registers are saved in memory not accessible to the program, and if the transaction is aborted, the saved contents are copied to the registers.
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公开(公告)号：US09311101B2
公开(公告)日：2016-04-12
申请号：US13524370
申请日：2012-06-15
CPC分类号： G06F9/3857 , G06F9/30 , G06F9/30043 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F9/466 , G06F9/467
摘要： Embodiments relate to intra-instructional transaction abort handling. An aspect includes using an emulation routine to execute an instruction within a transaction. The instruction includes at least one unit of operation. The transaction effectively delays committing stores to memory until the transaction has completed successfully. After receiving an abort indication, emulation of the instruction is terminated prior to completing the execution of the instruction. The instruction is terminated after the emulation routine completes any previously initiated unit of operation of the instruction.
摘要翻译： 实施例涉及教学内交易中止处理。 一方面包括使用仿真例程来执行事务内的指令。 该指令至少包含一个操作单元。 交易有效地延迟提交存储到内存，直到事务成功完成。 在接收到中止指示之后，在完成执行指令之前终止指令的仿真。 在仿真程序完成任何先前启动的指令的操作单元之后，指令终止。
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公开(公告)号：US09223687B2
公开(公告)日：2015-12-29
申请号：US13524342
申请日：2012-06-15
CPC分类号： G06F12/00 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3859 , G06F12/08 , G06F12/0808 , G06F12/0815 , G06F12/0822 , G06F12/0831 , G06F12/0833 , G06F12/0891
摘要： Embodiments relate to determining the logical address of a transaction abort. In an embodiment, one or more instructions are received are received from an application. The one or more instructions are executed within a first transaction. The first transaction delays committing stores to memory until it has completed. At least one of the one or more instructions includes a first logical memory address. The first logical memory address corresponds to a first memory address in a memory system. It is determined if the first memory address is equal to a second memory address that is stored in a conflict register. Based on determining that they are equal the first logical memory address is saved as a logical address associated with a cross invalidate (XI) signal at a location available to the application.
摘要翻译： 实施例涉及确定事务中止的逻辑地址。 在一个实施例中，从应用程序接收一个或多个接收的指令。 一个或多个指令在第一事务中执行。 第一个交易延迟将存储提交到内存，直到它完成。 所述一个或多个指令中的至少一个包括第一逻辑存储器地址。 第一逻辑存储器地址对应于存储器系统中的第一存储器地址。 确定第一存储器地址是否等于存储在冲突寄存器中的第二存储器地址。 基于确定它们相等，第一逻辑存储器地址被保存为与应用可用的位置处的交叉无效（XI）信号相关联的逻辑地址。
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79.发明授权Prefetch address translation using prefetch buffer based on availability of address translation logic 有权基于地址转换逻辑的可用性，使用预取缓冲区预取地址转换公开(公告)号：US09152566B2
公开(公告)日：2015-10-06
申请号：US13523919
申请日：2012-06-15
申请人： Khary J. Alexander , Ilia Averbouch , Ariel J. Birnbaum , Jonathan T. Hsieh , Christian Jacobi , Shmuel Paycher , Chung-Lung K. Shum
发明人： Khary J. Alexander , Ilia Averbouch , Ariel J. Birnbaum , Jonathan T. Hsieh , Christian Jacobi , Shmuel Paycher , Chung-Lung K. Shum
CPC分类号： G06F12/0862 , G06F12/1009
摘要： Embodiments relate to prefetch address translation in a computer processor. An aspect includes issuing, by prefetch logic, a prefetch request comprising a virtual page address. Another aspect includes, based on the prefetch request missing the TLB and the address translation logic of the processor being busy performing a current translation request, comparing a page of the prefetch request to a page of the current translation request. Yet another aspect includes, based on the page of the prefetch request matching the page of the current translation request, storing the prefetch request in a prefetch buffer.
摘要翻译： 实施例涉及计算机处理器中的预取地址转换。 一方面包括通过预取逻辑发出包括虚拟页面地址的预取请求。 另一方面包括：基于预取请求，丢失TLB，处理器的地址转换逻辑正在执行当前转换请求，将预取请求的页面与当前转换请求的页面进行比较。 另一方面包括：基于与当前转换请求的页面匹配的预取请求的页面，将预取请求存储在预取缓冲器中。
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公开(公告)号：US09052945B2
公开(公告)日：2015-06-09
申请号：US13524845
申请日：2012-06-15
摘要： A TRANSACTION BEGIN instruction and a TRANSACTION END instruction are provided. The TRANSACTION BEGIN instruction causes either a constrained or nonconstrained transaction to be initiated, depending on a field of the instruction. A constrained transaction has one or more restrictions associated therewith, while a nonconstrained transaction is not limited in the manner of a constrained transaction. The TRANSACTION END instruction ends the transaction started by the TRANSACTION BEGIN instruction.
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