公开(公告)号：US07355263B2

公开(公告)日：2008-04-08

申请号：US11763115

申请日：2007-06-14

申请人： Manabu Takei

发明人： Manabu Takei

IPC分类号： H01L29/00

CPC分类号： H01L29/42356 ,  H01L29/0649 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42324 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7396

摘要： A semiconductor device and method of manufacturing the same includes an n−-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode film doped in an n-type with an impurity concentration higher than that of the substrate as an n−-drift layer. In the cathode film, a section in contact with the substrate becomes an n+-buffer region with a high impurity concentration, next to which a p-base region is formed. Next to the p-base region, an n+-source region is formed. On the cathode film, an interlayer insulator film is selectively formed on which an emitter electrode is formed. A semiconductor device such as an IGBT is obtained with a high rate of acceptable products, an excellent on-voltage to turn-off loss tradeoff and an excellent on-voltage to breakdown voltage tradeoff.

摘要翻译： 半导体器件及其制造方法包括其上选择性地形成氧化物膜的单晶硅衬底。 在氧化膜上形成栅极多晶硅。 栅极多晶硅的表面被栅极氧化膜覆盖，该栅极氧化物膜的表面被杂质浓度高于衬底的n型掺杂的阴极膜覆盖，作为n型 层。 在阴极膜中，与衬底接触的部分成为具有高杂质浓度的n + +缓冲区，接着形成p基区。 在p基区旁边，形成n + SUP源源区。 在阴极膜上，选择性地形成层间绝缘膜，在其上形成发射电极。 以高速率的可接受的产品获得诸如IGBT的半导体器件，具有优异的导通电压到关断损耗折衷和优良的导通电压对击穿电压的折衷。

公开(公告)号：US07262478B2

公开(公告)日：2007-08-28

申请号：US11219308

申请日：2005-09-02

申请人： Manabu Takei

发明人： Manabu Takei

IPC分类号： H01L29/00

CPC分类号： H01L29/42356 ,  H01L29/0649 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/42324 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7396

摘要： A semiconductor device and method of manufacturing the same includes an n−-single crystal silicon substrate, with an oxide film selectively formed thereon. On the oxide film, gate polysilicon is formed. The surface of the gate polysilicon is covered with a gate oxide film whose surface is covered with a cathode film doped in an n-type with an impurity concentration higher than that of the substrate as an n−-drift layer. In the cathode film, a section in contact with the substrate becomes an n+-buffer region with a high impurity concentration, next to which a p-base region is formed. Next to the p-base region, an n+-source region is formed. On the cathode film, an interlayer insulator film is selectively formed on which an emitter electrode is formed. A semiconductor device such as an IGBT is obtained with a high rate of acceptable products, an excellent on-voltage to turn-off loss tradeoff and an excellent on-voltage to breakdown voltage tradeoff.

摘要翻译： 半导体器件及其制造方法包括其上选择性地形成氧化物膜的单晶硅衬底。 在氧化膜上形成栅极多晶硅。 栅极多晶硅的表面被栅极氧化膜覆盖，该栅极氧化物膜的表面被杂质浓度高于衬底的n型掺杂的阴极膜覆盖，作为n型 层。 在阴极膜中，与衬底接触的部分成为具有高杂质浓度的n + +缓冲区，接着形成p基区。 在p基区旁边，形成n + SUP源源区。 在阴极膜上，选择性地形成层间绝缘膜，在其上形成发射电极。 以高速率的可接受的产品获得诸如IGBT的半导体器件，具有优异的导通电压到关断损耗折衷和优良的导通电压对击穿电压的折衷。

公开(公告)号：US20070158740A1

公开(公告)日：2007-07-12

申请号：US11564053

申请日：2006-11-28

申请人： Koh Yoshikawa ,  Akio Sugi ,  Kouta Takahashi ,  Manabu Takei ,  Haruo Nakazawa ,  Noriyuki Iwamuro

发明人： Koh Yoshikawa ,  Akio Sugi ,  Kouta Takahashi ,  Manabu Takei ,  Haruo Nakazawa ,  Noriyuki Iwamuro

IPC分类号： H01L29/94 ,  H01L21/336

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor device including an n-type semiconductor substrate, a p-type channel region and a junction layer provided between the n-type semiconductor substrate and the p-type channel region is disclosed. The junction layer has n-type drift regions and p-type partition regions alternately arranged in the direction in parallel with the principal surface of the n-type semiconductor substrate. The p-type partition region forming the junction layer is made to have a higher impurity concentration than the n-type drift region. This enables the semiconductor device to have an enhanced breakdown voltage and, at the same time, have a reduced on-resistance.

摘要翻译： 公开了一种包括n型半导体衬底，p型沟道区和设置在n型半导体衬底和p型沟道区之间的结层的半导体器件。 接合层具有与n型半导体衬底的主表面平行的方向交替布置的n型漂移区和p型隔离区。 形成结层的p型分隔区的杂质浓度比n型漂移区高。 这使得半导体器件具有增强的击穿电压，并且同时具有降低的导通电阻。

公开(公告)号：US20060192204A1

公开(公告)日：2006-08-31

申请号：US11356407

申请日：2006-02-16

申请人： Ikuhiro Yamaguchi ,  Manabu Takei ,  Motohiko Yoshida

发明人： Ikuhiro Yamaguchi ,  Manabu Takei ,  Motohiko Yoshida

IPC分类号： H01L29/04

CPC分类号： H01L29/7869 ,  H01L27/1225 ,  H01L27/124

摘要： A thin film transistor panel including: a transparent substrate; scanning lines made of a light blocking electroconductive material to be formed on the transparent substrate; data lines formed on the transparent substrate to be perpendicular to the scanning lines and made of a light blocking electroconductive material; thin film transistors, each provided with a transparent gate electrode connected to one of the scanning lines, a transparent drain electrode connected to one of the data lines, a transparent source electrode and a transparent semiconductor thin film; and transparent pixel electrodes connected to the thin film transistors, wherein each of the pixel electrodes is formed to cover at least a part of the gate electrode of each of the thin film transistors.

摘要翻译： 一种薄膜晶体管板，包括：透明基板; 在透明基板上形成由阻光导电材料构成的扫描线; 在透明基板上形成垂直于扫描线并由阻光导电材料制成的数据线; 薄膜晶体管，每个薄膜晶体管均设有连接到扫描线之一的透明栅电极，连接到数据线之一的透明漏电极，透明源电极和透明半导体薄膜; 以及连接到薄膜晶体管的透明像素电极，其中每个像素电极形成为覆盖每个薄膜晶体管的栅电极的至少一部分。

公开(公告)号：US07049674B2

公开(公告)日：2006-05-23

申请号：US10822643

申请日：2004-04-12

申请人： Michio Nemoto ,  Manabu Takei ,  Tatsuya Naito

发明人： Michio Nemoto ,  Manabu Takei ,  Tatsuya Naito

IPC分类号： H01L21/8238 ,  H01L29/76

CPC分类号： H01L29/0646 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0834 ,  H01L29/404 ,  H01L29/7395

摘要： A reverse blocking semiconductor device that shows no adverse effect of an isolation region on reverse recovery peak current, that has a breakdown withstanding structure exhibiting satisfactory soft recovery, that suppresses aggravation of reverse leakage current, which essentially accompanies a conventional reverse blocking IGBT, and that retains satisfactorily low on-state voltage is disclosed. The device includes a MOS gate structure formed on a n− drift layer, the MOS gate structure including a p+ base layer formed in a front surface region of the drift layer, an n+ emitter region formed in a surface region of the base layer, a gate insulation film covering a surface area of the base layer between the emitter region and the drift layer, and a gate electrode formed on the gate insulation film. An emitter electrode is in contact with both the emitter region and the base layer of the MOS gate structure. A p+ isolation region surrounds the MOS gate structure through the drift layer and extends across whole thickness of the drift layer. A p+ collector layer is formed on a rear surface of the drift layer and connects to a rear side of the isolation region. A distance W is greater than a thickness d, in which the distance W is a distance from an outermost position of a portion of the emitter electrode, the portion being in contact with the base layer, to an innermost position of the isolation region, and the thickness d is a dimension in a depth direction of the drift layer.

公开(公告)号：US20050280613A1

公开(公告)日：2005-12-22

申请号：US11154961

申请日：2005-06-16

申请人： Manabu Takei ,  Tomoyuki Shirasaki ,  Ikuhiro Yamaguchi ,  Tsuyoshi Ozaki ,  Jun Ogura

发明人： Manabu Takei ,  Tomoyuki Shirasaki ,  Ikuhiro Yamaguchi ,  Tsuyoshi Ozaki ,  Jun Ogura

IPC分类号： G09G3/20 ,  G09G3/30

CPC分类号： G09G3/325 ,  G09G3/3266 ,  G09G3/3283 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0866 ,  G09G2310/0216 ,  G09G2310/0248 ,  G09G2310/0251 ,  G09G2310/027

摘要： A display device which displays image information based on display data comprising a display panel having a plurality of signal lines and scanning lines with a plurality of display pixels containing current control type light emitting devices; a scan driver circuit applies a scanning signal to each of the scanning lines and sets the display pixels connected to the scanning lines in a selective state; a signal driver circuit generates gradation current based on the display data luminosity gradation component and supplies to the display pixels set in the selective state; a precharge circuit applies a precharge voltage to each signal line and sets a capacity component attached to each of the scanning lines in a predetermined charged state; and an operation control circuit controls setting of the light emitting devices in a non-light emitting state when the capacity component is set in a predetermined charged state.

摘要翻译： 一种显示装置，其基于显示数据显示图像信息，所述显示数据包括具有多个信号线的显示面板和具有包含电流控制型发光装置的多个显示像素的扫描线; 扫描驱动器电路将扫描信号施加到每条扫描线，并将连接到扫描线的显示像素设置在选择状态; 信号驱动器电路基于显示数据亮度灰度分量产生灰度电流并提供给设置在选择状态的显示像素; 预充电电路对每个信号线施加预充电电压，并且以预定的充电状态设置附接到每个扫描线的电容分量; 并且当电容分量被设定在预定的充电状态时，操作控制电路控制发光器件在非发光状态下的设置。

公开(公告)号：US20050270259A1

公开(公告)日：2005-12-08

申请号：US11146814

申请日：2005-06-07

申请人： Tomoyuki Shirasaki ,  Tadahisa Tohyama ,  Manabu Takei ,  Jun Ogura ,  Ikuhiro Yamaguchi ,  Tsuyoshi Ozaki

发明人： Tomoyuki Shirasaki ,  Tadahisa Tohyama ,  Manabu Takei ,  Jun Ogura ,  Ikuhiro Yamaguchi ,  Tsuyoshi Ozaki

IPC分类号： G09G3/30 ,  G09G3/32 ,  H01L27/00 ,  H01L27/32

CPC分类号： H01L27/3279 ,  G09G3/325 ,  G09G2300/0842 ,  H01L27/3246 ,  H01L2227/323

摘要： A display device includes a substrate, and a light-emitting element which is provided on one side of the substrate. A pixel circuit is provided on the side of the substrate, and has at least one electrode to drive the light-emitting element. An interconnection is provided on the side of substrate, is electrically connected to the pixel circuit and has a conductive layer different from the electrode of the pixel circuit.

摘要翻译： 显示装置包括基板和设置在基板一侧的发光元件。 像素电路设置在基板一侧，并且具有驱动发光元件的至少一个电极。 在基板侧设置有互连，电连接到像素电路，并具有与像素电路的电极不同的导电层。

公开(公告)号：US20050219168A1

公开(公告)日：2005-10-06

申请号：US11093828

申请日：2005-03-29

申请人： Tomoyuki Shirasaki ,  Manabu Takei

发明人： Tomoyuki Shirasaki ,  Manabu Takei

IPC分类号： H05B33/12 ,  G09F9/00 ,  G09F9/30 ,  G09G3/00 ,  G09G3/20 ,  G09G3/30 ,  G09G3/32 ,  H01L51/50

CPC分类号： G09G3/006 ,  G09G3/2011 ,  G09G3/325 ,  G09G2300/0842 ,  G09G2320/0295 ,  G09G2320/043

摘要： A pixel circuit flows a current having a current value corresponding to a test voltage without intervening any display element.

摘要翻译： 像素电路流过具有对应于测试电压的电流值的电流，而不插入任何显示元件。

公开(公告)号：US06677626B1

公开(公告)日：2004-01-13

申请号：US09438077

申请日：1999-11-10

申请人： Youichi Shindou ,  Yasushi Miyasaka ,  Tatsuhiko Fujihira ,  Manabu Takei

发明人： Youichi Shindou ,  Yasushi Miyasaka ,  Tatsuhiko Fujihira ,  Manabu Takei

IPC分类号： C21B716

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/7802

摘要： This invention achieves a high inverse voltage of a super-junction semiconductor device, which has a drift layer composed of a parallel pn layer that conducts electricity in the ON state and is depleted in the OFF state. An n− high resistance region is formed at the periphery of a drift layer composed of a parallel pn layer of n drift regions and p partition regions. The impurity density ND of the n− high resistance region is 5.62×1017×VDSS−1.36(cm−3) or less. VDSS denotes the withstand voltage (V). An n low resistance region is arranged adjacent to the n− high resistance region.

摘要翻译： 本发明实现了超结半导体器件的高反向电压，其具有由并联pn层构成的漂移层，该pn层在导通状态下导通并且被截止状态。 在由n个漂移区域和p个分割区域的并行pn层构成的漂移层的周围形成n 高电阻区域。 n高电阻区域的杂质浓度ND为5.62×10 17 xVDSS <-1.36（cm -3）以下。 VDSS表示耐压（V）。 n个低电阻区域被布置成与n +高电阻区域相邻。

公开(公告)号：US6046788A

公开(公告)日：2000-04-04

申请号：US73636

申请日：1998-05-06

申请人： Tomio Tanaka ,  Tetsushi Yoshida ,  Manabu Takei ,  Jun Ogura

发明人： Tomio Tanaka ,  Tetsushi Yoshida ,  Manabu Takei ,  Jun Ogura

IPC分类号： G02F1/1337 ,  G02F1/133 ,  G02F1/141 ,  G09F9/35

CPC分类号： G02F1/141

摘要： A liquid crystal material is sealed between substrates. The liquid crystal material exhibits an antiferroelectric phase while the liquid crystal is in a bulk state. In the liquid crystal layer sealed between the substrates, due to aligning forces of alignment films, liquid crystal molecules are aligned in a state wherein there is no correlation in molecular order between adjoining smectic layers, and the director of the liquid crystal layer is substantially coincident with the direction of a normal line of the smectic layers. The director varies continuously in accordance with the polarity and magnitude of a voltage applied between electrodes formed on the substrates. Arranging polarization plates so that the substrates are sandwiched therebetween enables a gradation to be displayed.

摘要翻译： 液晶材料被密封在基板之间。 当液晶处于大量状态时，液晶材料呈现反铁电相。 在密封在基板之间的液晶层中，由于取向膜的取向力，液晶分子在相邻的近晶层之间的分子顺序无相关性的状态下排列，液晶层的指向基本一致 随着近晶层的正常线的方向。 导向器根据在基板上形成的电极之间施加的电压的极性和大小而连续变化。 排列偏光板使基板夹在两者之间能够显示灰度。