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    Electrostatic discharge protection circuit using triple welled silicon controlled rectifier
    71.
    发明授权
    Electrostatic discharge protection circuit using triple welled silicon controlled rectifier 有权
    静电放电保护电路采用三芯硅控整流器

    公开(公告)号：US07576961B2

    公开(公告)日：2009-08-18

    申请号：US12018317

    申请日：2008-01-23

    申请人： Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

    发明人： Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

    IPC分类号： H02H9/00 ,  H01L23/62

    CPC分类号： H01L29/7436 ,  H01L29/749 ,  H01L29/87 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a trigger voltage of the SCR is reduced. In addition, two discharge paths are formed using two SCRs including PNP and NPN bipolar transistors. As a result, the ESD protection circuit can have greater discharge capacity.

    摘要翻译： 提供了一种应用于半导体集成电路（IC）的使用可控硅整流器（SCR）的静电放电（ESD）保护电路。 半导体衬底具有三重阱结构，使得偏置被施加到对应于ggNMOS器件的衬底的p阱。 因此，SCR的触发电压降低。 此外，使用包括PNP和NPN双极晶体管的两个SCR形成两个放电路径。 因此，ESD保护电路可以具有更大的放电容量。

    Low-power clock gating circuit
    72.
    发明授权
    Low-power clock gating circuit 有权
    低功耗时钟门控电路

    公开(公告)号：US07576582B2

    公开(公告)日：2009-08-18

    申请号：US11945387

    申请日：2007-11-27

    申请人： Dae Woo Lee ,  Yil Suk Yang ,  Ik Jae Chun ,  Chun Gi Lyuh ,  Tae Moon Roh ,  Jong Dae Kim

    发明人： Dae Woo Lee ,  Yil Suk Yang ,  Ik Jae Chun ,  Chun Gi Lyuh ,  Tae Moon Roh ,  Jong Dae Kim

    IPC分类号： H03K3/289

    CPC分类号： H03K3/0375

    摘要： Provided is a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The low-power clock gating circuit includes a latch circuit of an input stage and an AND gate circuit of an output stage, in which power consumption caused by leakage current in the clock gating circuit is reduced in a sleep mode, and supply of a clock to a unused device of a targeted logic circuit is prevented by the control of a clock enable signal in an active mode, thereby reducing power consumption. The low-power clock gating circuit using an MTCMOS technique uses devices having a low threshold voltage and devices having a high threshold voltage, which makes it possible to implement a high-speed, low-power circuit, unlike a conventional clock gating circuit using a single threshold voltage.

    摘要翻译： 提供了使用多阈值CMOS（MTCMOS）技术的低功率时钟选通电路。 低功率时钟选通电路包括输入级的锁存电路和输出级的与门电路，其中由休眠模式中的时钟门控电路中的漏电流引起的功耗降低，并且提供时钟 通过控制活动模式中的时钟使能信号来防止目标逻辑电路的未使用的装置，从而降低功耗。 使用MTCMOS技术的低功率时钟选通电路使用具有低阈值电压的器件和具有高阈值电压的器件，这使得可以实现高速，低功率电路，这与使用 单阈值电压。

    Multi-bit delta-sigma modulator
    73.
    发明授权
    Multi-bit delta-sigma modulator 有权
    多位delta-Σ调制器

    公开(公告)号：US07545301B2

    公开(公告)日：2009-06-09

    申请号：US11950481

    申请日：2007-12-05

    申请人： Yi Gyeong Kim ,  Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

    发明人： Yi Gyeong Kim ,  Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

    IPC分类号： H03M3/00

    CPC分类号： H03M3/374 ,  H03M3/338 ,  H03M3/424 ,  H03M3/45 ,  H03M3/452 ,  H03M3/454

    摘要： A delta-sigma modulator having a first integrator for integrating an input signal; an analog-to-digital converter for converting the integrated signal into a digital signal; a delay circuit for delaying an output signal of the analog-to-digital converter; and a differential delay circuit for differentially delaying the output signal of the analog-to-digital converter. More particularly, the delta-sigma modulator has low distortion characteristics suitable for multi-bit fast operation, wherein a feedback signal is delayed by one clock period through the delay circuit and the differential delay circuit.

    摘要翻译： 一种Δ-Σ调制器，具有用于积分输入信号的第一积分器; 用于将积分信号转换为数字信号的模拟 - 数字转换器; 延迟电路，用于延迟模数转换器的输出信号; 以及用于差分地延迟模数转换器的输出信号的差分延迟电路。 更具体地，Δ-Σ调制器具有适合于多位快速操作的低失真特性，其中通过延迟电路和差分延迟电路将反馈信号延迟一个时钟周期。

    Multi-threshold CMOS latch circuit
    74.
    发明授权
    Multi-threshold CMOS latch circuit 失效
    多阈值CMOS锁存电路

    公开(公告)号：US07391249B2

    公开(公告)日：2008-06-24

    申请号：US11607743

    申请日：2006-12-01

    申请人： Dae Woo Lee ,  Yil Suk Yang ,  Gyu Hyun Kim ,  Soon Il Yeo ,  Jong Dae Kim

    发明人： Dae Woo Lee ,  Yil Suk Yang ,  Gyu Hyun Kim ,  Soon Il Yeo ,  Jong Dae Kim

    IPC分类号： H03K3/289

    CPC分类号： H03K3/356156 ,  H03K3/012

    摘要： Provided is a multi-threshold complementary metal oxide semiconductor (MTCMOS) latch circuit including: a data inverting circuit for inverting and outputting input data under the control of a sleep control signal; a transmission gate for transferring the data signal output from the data inverting circuit under the control of a clock control signal; a signal control circuit for outputting the data signal output from the transmission gate under the control of a reset control signal and the sleep control signal; and a feedback circuit for feeding back the signal output from the signal control circuit and preserving the data in a sleep mode. The MTCMOS latch circuit can minimize power consumption caused by a leakage current due to elements scaled down to nano scale and also contribute to high-speed operation of a logic circuit by using an element having a low threshold voltage.

    摘要翻译： 提供了一种多阈值互补金属氧化物半导体（MTCMOS）锁存电路，包括：数据反相电路，用于在睡眠控制信号的控制下反相输出输入数据; 传输门，用于在时钟控制信号的控制下传送从数据反相电路输出的数据信号; 信号控制电路，用于在复位控制信号和睡眠控制信号的控制下输出从传输门输出的数据信号; 以及用于反馈从信号控制电路输出的信号并且以睡眠模式保存数据的反馈电路。 MTCMOS锁存电路可以将由于按比例缩小到纳米级的元件引起的漏电流引起的功耗最小化，并且还通过使用具有低阈值电压的元件有助于逻辑电路的高速操作。

    Arithmetic method and device of reconfigurable processor
    76.
    发明申请
    Arithmetic method and device of reconfigurable processor 失效
    可重构处理器的算术方法和装置

    公开(公告)号：US20080140745A1

    公开(公告)日：2008-06-12

    申请号：US11978878

    申请日：2007-10-30

    申请人： Chun Gi Lyuh ,  Soon Il Yeo ,  Tae Moon Roh ,  Jong Dae Kim

    发明人： Chun Gi Lyuh ,  Soon Il Yeo ,  Tae Moon Roh ,  Jong Dae Kim

    IPC分类号： G06F5/01

    CPC分类号： G06F7/57

    摘要： Provided are an arithmetic method and device of a reconfigurable processor. The arithmetic device includes: an Arithmetic Logic Unit (ALU) for performing an addition and subtraction operation and a logic operation of a binary signal; a multiplier for performing a multiplication operation of the binary signal; a shifter for changing an arrangement of the binary signal; a first operand selector and a second operand selector each for selecting one of values output from the ALU, the multiplier, and the shifter; and an adder for adding the values selected by the first operand selector and the second operand selector.

    摘要翻译： 提供了可重构处理器的算术方法和装置。 算术装置包括：用于执行加法运算和减法运算的算术逻辑单元（ALU）和二进制信号的逻辑运算; 用于执行二进制信号的乘法运算的乘法器; 用于改变二进制信号的布置的移位器; 每个用于选择从所述ALU，所述乘法器和所述移位器输出的值之一的第一操作数选择器和第二操作数选择器; 以及用于将由第一操作数选择器和第二操作数选择器选择的值相加的加法器。

    CONDENSER MICROPHONE HAVING FLEXURE HINGE DIAPHRAGM AND METHOD OF MANUFACTURING THE SAME
    77.
    发明申请
    CONDENSER MICROPHONE HAVING FLEXURE HINGE DIAPHRAGM AND METHOD OF MANUFACTURING THE SAME 失效
    具有挠性铰链膜片的冷凝器麦克风及其制造方法

    公开(公告)号：US20080137884A1

    公开(公告)日：2008-06-12

    申请号：US11875996

    申请日：2007-10-22

    申请人： Hye Jin KIM ,  Sung Q. Lee ,  Kang Ho Park ,  Jong Dae Kim

    发明人： Hye Jin KIM ,  Sung Q. Lee ,  Kang Ho Park ,  Jong Dae Kim

    IPC分类号： H04R25/00 ,  H01L21/64

    CPC分类号： H04R31/003 ,  H04R19/005 ,  H04R31/00 ,  H04R2499/11

    摘要： A micromini condenser microphone having a flexure hinge-shaped upper diaphragm and a back plate, and a method of manufacturing the same are provided.The method includes the steps of: forming a lower silicon layer and a first insulating layer; forming an upper silicon layer to be used as a back plate on the first insulating layer; forming a plurality of sound holes by patterning the upper silicon layer; forming a second insulating layer on the upper silicon layer; forming a conductive layer on the upper silicon layer having the sound holes, and forming a passivation layer on the conductive layer; forming a sacrificial layer on the passivation layer; depositing a diaphragm on the sacrificial layer, and forming a plurality of air holes passing through the diaphragm; forming electrode pads on the passivation layer and a region of the diaphragm; and etching the sacrificial layer, the passivation layer, the conductive layer, the upper silicon layer, the first insulating layer and the lower silicon layer to form an air gap between the diaphragm and the upper silicon layer.Consequently, due to the flexible diaphragm, a manufacturing process using semiconductor MEMS technology may improve the sensitivity of the condenser microphone and reduce the size of the condenser microphone, thereby enabling integration into a portable terminal.

    摘要翻译： 提供具有弯曲铰链形上隔膜和背板的微型电容麦克风及其制造方法。 该方法包括以下步骤：形成下硅层和第一绝缘层; 在所述第一绝缘层上形成用作背板的上硅层; 通过图案化上硅层形成多个声孔; 在所述上硅层上形成第二绝缘层; 在具有所述声孔的所述上硅层上形成导电层，并在所述导电层上形成钝化层; 在钝化层上形成牺牲层; 在所述牺牲层上沉积隔膜，以及形成通过所述隔膜的多个空气孔; 在所述钝化层上形成电极焊盘和所述隔膜的区域; 蚀刻牺牲层，钝化层，导电层，上硅层，第一绝缘层和下硅层，以在隔膜和上硅层之间形成气隙。 因此，由于柔性隔膜，使用半导体MEMS技术的制造工艺可以提高电容式麦克风的灵敏度并减小电容式麦克风的尺寸，从而可以集成到便携式终端中。

    DYE-SENSITIZED SOLAR CELL MODULE HAVING VERTICALLY STACKED CELLS AND METHOD OF MANUFACTURING THE SAME
    78.
    发明申请
    DYE-SENSITIZED SOLAR CELL MODULE HAVING VERTICALLY STACKED CELLS AND METHOD OF MANUFACTURING THE SAME 审中-公开
    具有垂直堆积细胞的透明的太阳能电池模块及其制造方法

    公开(公告)号：US20080115824A1

    公开(公告)日：2008-05-22

    申请号：US11774349

    申请日：2007-07-06

    申请人： Mangu Kang ,  Soo Young Oh ,  Yongseok Jun ,  Jong Dae Kim

    发明人： Mangu Kang ,  Soo Young Oh ,  Yongseok Jun ,  Jong Dae Kim

    IPC分类号： H01L31/052

    CPC分类号： H01G9/2068 ,  H01G9/2031 ,  H01G9/2059 ,  H01G9/2072 ,  Y02E10/542 ,  Y02E10/549 ,  Y02P70/521

    摘要： Provided are a dye-sensitized solar cell module having a vertically stacked cell structure and a method of manufacturing the same. In the dye-sensitized solar cell module, a plurality of cells are vertically stacked in parallel with each other. Each of the cells includes mutually facing semiconductor and counter electrodes and an electrolyte layer interposed between the semiconductor and counter electrodes. A first conductive transparent substrate is interposed between two neighboring cells of the cells. The first conductive transparent substrate includes a first surface on which the counter electrode of one of the two neighboring cells is formed and a second surface on which the semiconductor electrode of the other is formed. A second conductive transparent substrate having a semiconductor electrode forms the lowermost cell of the cells, and a third conductive transparent substrate having a counter electrode forms the uppermost cell of the cells.

    摘要翻译： 提供具有垂直堆叠的电池结构的染料敏化太阳能电池模块及其制造方法。 在染料敏化太阳能电池模块中，多个电池彼此平行地垂直堆叠。 每个电池包括相互面对的半导体和对电极以及插入在半导体和对电极之间的电解质层。 第一导电透明衬底插入在电池的两个相邻电池之间。 第一导电透明基板包括形成两个相邻单元之一的对电极的第一表面和形成另一个的半导体电极的第二表面。 具有半导体电极的第二导电透明基板形成单元的最下面的单元，具有对电极的第三导电透明基板形成单元的最上面的单元。

    Electrostatic discharge protection circuit using triple welled silicon controlled rectifier
    79.
    发明授权
    Electrostatic discharge protection circuit using triple welled silicon controlled rectifier 有权
    静电放电保护电路采用三芯硅控整流器

    公开(公告)号：US07342281B2

    公开(公告)日：2008-03-11

    申请号：US11294255

    申请日：2005-12-05

    申请人： Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

    发明人： Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim

    IPC分类号： H01L23/62

    CPC分类号： H01L29/7436 ,  H01L29/749 ,  H01L29/87 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Provided is an electrostatic discharge (ESD) protection circuit using a silicon controlled rectifier (SCR), which is applied to a semiconductor integrated circuit (IC). A semiconductor substrate has a triple well structure such that a bias is applied to a p-well corresponding to a substrate of a ggNMOS device. Thus, a trigger voltage of the SCR is reduced. In addition, two discharge paths are formed using two SCRs including PNP and NPN bipolar transistors. As a result, the ESD protection circuit can have greater discharge capacity.

    摘要翻译： 提供了一种应用于半导体集成电路（IC）的使用可控硅整流器（SCR）的静电放电（ESD）保护电路。 半导体衬底具有三重阱结构，使得偏置被施加到对应于ggNMOS器件的衬底的p阱。 因此，SCR的触发电压降低。 此外，使用包括PNP和NPN双极晶体管的两个SCR形成两个放电路径。 因此，ESD保护电路可以具有更大的放电容量。