公开(公告)号：US20080100357A1

公开(公告)日：2008-05-01

申请号：US11978636

申请日：2007-10-30

申请人： Seung-Jun Bae

发明人： Seung-Jun Bae

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0812 ,  H03L7/0818 ,  H03L7/087 ,  H03L7/10

摘要： A delay locked loop (DLL) circuit includes a basic loop, a coarse loop, a delay model and a fine loop. The basic loop generates a plurality of first clock signals, based at least in part on an input clock signal, a feedback clock signal and a fine loop output signal. The first clock signals respectively have a phase difference. The coarse loop generates a plurality of output clock signals, based at least in part on the input clock signal, the feedback clock signal and the first clock signals. The plurality of output clock signals respectively have a phase difference. The delay model generates the feedback clock signal by delaying one of the output clock signals by a first time period. The fine loop generates the fine loop output signal, based at least in part on the input clock signal and the feedback clock signal.

摘要翻译： 延迟锁定环（DLL）电路包括基本循环，粗循环，延迟模型和精细循环。 至少部分地基于输入时钟信号，反馈时钟信号和精细回路输出信号，基本回路产生多个第一时钟信号。 第一时钟信号分别具有相位差。 至少部分地基于输入时钟信号，反馈时钟信号和第一时钟信号，粗略回路产生多个输出时钟信号。 多个输出时钟信号分别具有相位差。 延迟模型通过将输出时钟信号之一延迟第一时间段来产生反馈时钟信号。 至少部分地基于输入时钟信号和反馈时钟信号，精细循环产生精细环路输出信号。

公开(公告)号：US20070242508A1

公开(公告)日：2007-10-18

申请号：US11730795

申请日：2007-04-04

申请人： Seung-Jun Bae

发明人： Seung-Jun Bae

IPC分类号： G11C11/34

CPC分类号： G11C7/1006 ,  G11C7/02 ,  G11C7/1048 ,  G11C11/406

摘要： A method and apparatus for reducing power consumption needed to refresh a memory may receive data having been encoded using data bus inversion (DBI), the DBI data having a first delta between a number of zeros for different cases between zero and a DBI maximum, balance code the DBI data to balance the number of zeros across the DBI data, and output data having a number of zeros for different cases between a minimum number greater than zero and less than or equal to the DBI maximum and a maximum number equal to the minimum number plus a second delta, the second delta being less than the first delta.

摘要翻译： 用于减少刷新存储器所需的功率消耗的方法和装置可以接收已经使用数据总线反转（DBI）编码的数据，DBI数据具有在零和DBI最大值之间的不同情况下的零个数之间的第一增量，余额 对DBI数据进行编码以平衡DBI数据上的零数，并且输出具有大于零且小于或等于DBI最大值的最小数量和等于最小值的最大数量的不同情况下的零个数的数据 数字加上第二个delta，第二个delta小于第一个delta。

公开(公告)号：US08339877B2

公开(公告)日：2012-12-25

申请号：US12764460

申请日：2010-04-21

申请人： Sang-Hyup Kwak ,  Seung-Jun Bae ,  Young-Sik Kim

发明人： Sang-Hyup Kwak ,  Seung-Jun Bae ,  Young-Sik Kim

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  G11C29/4401 ,  G11C29/50012 ,  G11C2207/2254

摘要： A semiconductor memory device comprises a variable delay unit and a data trainer. The variable delay unit is configured to generate a write data signal by delaying a write data driving signal by different amounts of time depending on whether the semiconductor memory device is in a data training mode or a normal operating mode, and further configured to generate a read data driving signal by delaying a read data signal by different amounts of time in the data training mode and the normal operating mode. The data trainer is configured to be activated in the data training mode, and while activated, receive the write data signal, compare the write data signal with a predetermined write pattern, perform a data training mode operation, and output the read data signal with a predetermined read pattern.

摘要翻译： 半导体存储器件包括可变延迟单元和数据训练器。 可变延迟单元被配置为根据半导体存储器件是处于数据训练模式还是正常操作模式，通过将写入数据驱动信号延迟不同的时间量来产生写入数据信号，并且还被配置为产生读取 数据驱动信号，通过在数据训练模式和正常操作模式下延迟读取数据信号不同的时间量。 数据训练器被配置为在数据训练模式下被激活，并且被激活时，接收写入数据信号，将写入数据信号与预定的写入模式进行比较，执行数据训练模式操作，并将读出的数据信号输出 预定的读取模式。

公开(公告)号：US20120063242A1

公开(公告)日：2012-03-15

申请号：US13162948

申请日：2011-06-17

申请人： DAE-HYUN KIM ,  Seung-Jun Bae

发明人： DAE-HYUN KIM ,  Seung-Jun Bae

IPC分类号： G11C7/10

CPC分类号： G11C7/1012 ,  G11C7/1048 ,  G11C7/1084 ,  G11C7/1087

摘要： A data receiver in a memory device includes an integration unit, a sense amplification unit and a latch unit. The integration unit integrates a data signal to generate a first equalization signal in response to a sampling feedback signal. The data signal includes a plurality of data that are sequentially received. The sense amplification unit senses the first equalization signal to generate a second equalization signal in response to a sensing feedback signal. The latch unit latches the second equalization signal to generate a sampling data signal

摘要翻译： 存储器件中的数据接收器包括积分单元，感测放大单元和锁存单元。 积分单元积分数据信号，以响应于采样反馈信号产生第一均衡信号。 数据信号包括顺序接收的多个数据。 感测放大单元响应于感测反馈信号感测第一均衡信号以产生第二均衡信号。 锁存单元锁存第二均衡信号以产生采样数据信号

公开(公告)号：US20110310659A1

公开(公告)日：2011-12-22

申请号：US13109157

申请日：2011-05-17

申请人： Ho-Seok Seol ,  Seung-Jun Bae ,  Sang-Hyup Kwak

发明人： Ho-Seok Seol ,  Seung-Jun Bae ,  Sang-Hyup Kwak

IPC分类号： G11C11/24 ,  H03B5/12 ,  H03B7/06

CPC分类号： H03B5/1228 ,  G11C7/222 ,  H03B5/1215 ,  H03B5/124

摘要： A voltage-controlled oscillator includes an oscillating unit configured to output first and second output clock signals at first and second nodes, respectively, the first and second output clock signals having a frequency that is variable in response to a control voltage. An active element unit connected to the oscillating unit is configured to maintain oscillation of the oscillating unit. A bias current generating unit connected to the active element unit at a bias node provides a bias current to the bias node and is adapted to adjust the bias current in response to a control code. First and second capacitor blocks connected to the oscillating unit and the active element unit provide first and second load capacitances, respectively, to the first and second nodes, respectively, in response to the control code.

摘要翻译： 压控振荡器包括：振荡单元，被配置为分别在第一和第二节点处输出第一和第二输出时钟信号，第一和第二输出时钟信号具有响应于控制电压而变化的频率。 连接到振荡单元的有源元件单元被配置为保持振荡单元的振荡。 在偏置节点处连接到有源元件单元的偏置电流产生单元向偏置节点提供偏置电流，并且适于响应于控制代码调整偏置电流。 连接到振荡单元和有源元件单元的第一和第二电容器块分别响应于控制代码分别向第一和第二节点提供第一和第二负载电容。

公开(公告)号：US07957497B2

公开(公告)日：2011-06-07

申请号：US11938810

申请日：2007-11-13

申请人： Seung-Jun Bae

发明人： Seung-Jun Bae

IPC分类号： H04L7/00

CPC分类号： H04L7/0337

摘要： A clock and data recovery (CDR) circuit comprises a data sampling unit which latches serial data input in response to data clock signals, and outputs a plurality of sampling data, the data clock signals maintaining a constant phase difference and having mutually different phases, an edge sampling unit which outputs an edge sampling signal generated by sampling edge information of the serial data in response to a selection edge clock signal, the selection edge clock signal being randomly selected from among a plurality of edge clock signals, a data selection unit which selects at least two consecutive sampling data from among the plurality of sampling data, and a decoding unit which performs a logical operation of the sampling data selected by the data selection unit and the edge sampling signal.

摘要翻译： 时钟和数据恢复（CDR）电路包括数据采样单元，其响应于数据时钟信号锁存串行数据输入，并输出多个采样数据，数据时钟信号维持恒定的相位差并具有相互不同的相位， 边缘采样单元，其响应于选择边沿时钟信号输出通过对串行数据的边缘信息进行采样而产生的边缘采样信号，从多个边缘时钟信号中随机选择选择边沿时钟信号;数据选择单元，其选择 来自多个采样数据中的至少两个连续采样数据，以及执行由数据选择单元选择的采样数据和边缘采样信号的逻辑运算的解码单元。

公开(公告)号：US20100141311A1

公开(公告)日：2010-06-10

申请号：US12627730

申请日：2009-11-30

申请人： Young-Sik Kim ,  Seung-Jun Bae ,  Sang-Hyup Kwak

发明人： Young-Sik Kim ,  Seung-Jun Bae ,  Sang-Hyup Kwak

IPC分类号： H03L7/06 ,  H03K3/01

CPC分类号： H03L7/08

摘要： A phase-locked loop (PLL) having a bias generator capable of reducing noise is provided. In the PLL, a voltage controlled oscillator is driven using a regulator. The bias generator, which applies a bias voltage to the regulator, is configured to have opposite power noise characteristics to the power noise characteristics of the regulator, such that the occurrence of jitter in the PLL is reduced.

摘要翻译： 提供了具有能够降低噪声的偏置发生器的锁相环（PLL）。 在PLL中，使用稳压器驱动压控振荡器。 将偏置电压施加到调节器的偏置发生器被配置为具有与调节器的功率噪声特性相反的功率噪声特性，使得PLL中的抖动的发生减少。

公开(公告)号：US07701257B2

公开(公告)日：2010-04-20

申请号：US11870482

申请日：2007-10-11

申请人： Seung-Jun Bae

发明人： Seung-Jun Bae

IPC分类号： G01R19/00 ,  G11C7/00 ,  H03F3/45

CPC分类号： G11C7/1078 ,  G11C7/1087 ,  G11C11/4093

摘要： The invention is directed to data receivers such as those used in semiconductor devices. Embodiments of the invention provide a loop unrolling DFE receiver that uses analog control signals from each equalizer to avoid timing delays associated with the use of latched digital control signals in the conventional art. In addition, embodiments of the invention implement each equalizer with a single sense amplifier based flip flop (SAFF) to reduce circuit size and power consumption.

摘要翻译： 本发明涉及诸如在半导体器件中使用的数据接收器。 本发明的实施例提供一种循环展开的DFE接收机，其使用来自每个均衡器的模拟控制信号来避免与传统技术中使用锁存的数字控制信号相关联的定时延迟。 此外，本发明的实施例用基于单个读出放大器的触发器（SAFF）来实现每个均衡器以减小电路尺寸和功耗。

公开(公告)号：US07649389B2

公开(公告)日：2010-01-19

申请号：US11978636

申请日：2007-10-30

申请人： Seung-Jun Bae

发明人： Seung-Jun Bae

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03L7/0812 ,  H03L7/0818 ,  H03L7/087 ,  H03L7/10

摘要： A delay locked loop (DLL) circuit includes a basic loop, a coarse loop, a delay model and a fine loop. The basic loop generates a plurality of first clock signals, based at least in part on an input clock signal, a feedback clock signal and a fine loop output signal. The first clock signals respectively have a phase difference. The coarse loop generates a plurality of output clock signals, based at least in part on the input clock signal, the feedback clock signal and the first clock signals. The plurality of output clock signals respectively have a phase difference. The delay model generates the feedback clock signal by delaying one of the output clock signals by a first time period. The fine loop generates the fine loop output signal, based at least in part on the input clock signal and the feedback clock signal.

摘要翻译： 延迟锁定环（DLL）电路包括基本循环，粗循环，延迟模型和精细循环。 至少部分地基于输入时钟信号，反馈时钟信号和精细回路输出信号，基本回路产生多个第一时钟信号。 第一时钟信号分别具有相位差。 至少部分地基于输入时钟信号，反馈时钟信号和第一时钟信号，粗略回路产生多个输出时钟信号。 多个输出时钟信号分别具有相位差。 延迟模型通过将输出时钟信号之一延迟第一时间段来产生反馈时钟信号。 至少部分地基于输入时钟信号和反馈时钟信号，精细循环产生精细环路输出信号。

公开(公告)号：US20080048730A1

公开(公告)日：2008-02-28

申请号：US11878062

申请日：2007-07-20

申请人： Seung-Jun Bae

发明人： Seung-Jun Bae

IPC分类号： H03K5/22

CPC分类号： H03K5/2481 ,  G06F13/4072

摘要： A single ended pseudo differential signaling method may add a 1-bit signal to n-bit data if transmitting the n-bit data. Neighboring two signals among the 1-bit signal and data signals are compared to each other to generate detection signals.

摘要翻译： 如果发送n位数据，则​​单端伪差分信令方法可以将1位信号添加到n位数据。 将1比特信号和数据信号中的相邻两个信号相互比较以产生检测信号。