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公开(公告)号：US10404283B2
公开(公告)日：2019-09-03
申请号：US15259065
申请日：2016-09-08
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang
Abstract: A method for decoding an error correction code and an associated decoding circuit are provided, where the method includes the steps of: calculating a set of error syndromes of the error correction code, where the error correction code is a t-error correcting code and has capability of correcting t errors, and a number s of the set of error syndromes is smaller than t; sequentially determining a set of coefficients within a plurality of coefficients of an error locator polynomial of the error correction code according to at least one portion of error syndromes within the set of error syndromes for building a roughly-estimated error locator polynomial; performing a Chien search to determine a plurality of roots of the roughly-estimated error locator polynomial; and performing at least one check operation to selectively utilize a correction result of the error correction code as a decoding result of the error correction code.
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公开(公告)号：US20190155531A1
公开(公告)日：2019-05-23
申请号：US16260142
申请日：2019-01-29
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Chun-Chieh Kuo , Ching-Hui Lin , Yang-Chih Shen
CPC classification number: G06F3/0634 , G06F3/0604 , G06F3/064 , G06F3/0679 , G06F12/0246 , G06F2212/7201 , G06F2212/7206 , G11C11/5628 , G11C11/5642 , Y02D10/13
Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
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73.发明授权公开(公告)号：US10289487B2
公开(公告)日：2019-05-14
申请号：US15495993
申请日：2017-04-25
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Hong-Jung Hsu
Abstract: A method for accessing a flash memory module is provided. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least a first super block and at least a second super block of the flash memory chips; and allocating the second super block to store a plurality of temporary parities generated when data is written into the first super block.
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74.发明申请公开(公告)号：US20190089374A1
公开(公告)日：2019-03-21
申请号：US16194374
申请日：2018-11-18
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Jian-Dong Du
Abstract: A method for performing low-density parity check (LDPC) decoding includes: in a first decoder which operates in a first mode, performing a plurality of decoding iterations of a codeword using a first algorithm, including: decoding the codeword to generate first information including a number of failed check nodes; linking the number of failed check nodes to a log-likelihood ratio (LLR) value to generate second information; and performing parity check equations for the codeword at check nodes. When a predetermined number of decoding iterations in the first decoder is reached without the parity check equations being solved, decoding of the codeword using the first decoder is stopped, the codeword is input to a second decoder and decoding of the codeword in the second decoder using a second algorithm and the second information is started.
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公开(公告)号：US10236908B2
公开(公告)日：2019-03-19
申请号：US15495992
申请日：2017-04-25
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Hong-Jung Hsu
Abstract: A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programming and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.
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Patent Agency Ranking
公开(公告)号：US10199110B2
公开(公告)日：2019-02-05
申请号：US15852847
申请日：2017-12-22
Applicant: Silicon Motion, Inc.
Inventor： Tsung-Chieh Yang
Abstract: A method for reading data stored in a flash memory. The flash memory comprises a plurality of memory cells and each memory cell has a particular threshold voltage. The method includes: obtaining a first threshold voltage distribution representing threshold voltages of a first group of the memory cells; obtaining a second threshold voltage distribution representing threshold voltages of a second group of the memory cells, wherein the second threshold voltage distribution is different from the first threshold voltage distribution, and the first group of the memory cells comprises at least a part of the second group of the memory cells; and controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to the second threshold voltage distribution.
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公开(公告)号：US20190027214A1
公开(公告)日：2019-01-24
申请号：US16127240
申请日：2018-09-11
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Hsiao-Te Chang , Wen-Long Wang
Abstract: A Flash memory access module performs memory access management of a Flash storage device including a plurality of storage cells. The Flash memory access module includes: a read only memory for storing a program code; and a microprocessor which executes the program code to perform the following steps: performing a first sensing operation corresponding to a first sensing voltage in a storage cell, and performing a second sensing operation in the storage cell; using the first sensing operation and at least the second sensing operation to generate a first digital value and a second digital value, respectively, of the storage cell; using the first digital value and the second digital value to obtain soft information of a same bit stored in the storage cell; and using the soft information to perform soft decoding.
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公开(公告)号：US20180341545A1
公开(公告)日：2018-11-29
申请号：US16053815
申请日：2018-08-03
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Sheng-I Hsu
Abstract: A data storage system includes a processing circuit, a lookup table (LUT), and a decoding circuit. The processing circuit is arranged to receive a first logical block address (LBA) from a host. The LUT is arranged to store a storage address mapping to the first LBA. The decoding circuit is arranged to utilize the storage address to read storage data from a storing circuit, and decode a first data sector in the storage data according to an error checking and correcting code in the storage data, and the first data sector at least comprises a second LBA.
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79.发明授权公开(公告)号：US10133664B2
公开(公告)日：2018-11-20
申请号：US15497217
申请日：2017-04-26
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Hong-Jung Hsu
IPC: G06F12/02 , G06F3/06 , G06F11/10 , G11C7/10 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/26 , G11C29/52 , G11C16/08
Abstract: A method for accessing a flash memory module is provide. The flash memory module is a 3D flash memory module including a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, each block includes a plurality of pages, and the method includes: configuring the flash memory chips to set at least one super block of the flash memory chips; and allocating a buffer memory space to store a plurality of temporary parities generated when data is written into the at least one first super block.
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公开(公告)号：US10102904B2
公开(公告)日：2018-10-16
申请号：US15679178
申请日：2017-08-17
Applicant: Silicon Motion Inc.
Inventor： Tsung-Chieh Yang , Hsiao-Te Chang , Wen-Long Wang
Abstract: A memory access module for performing memory access management of a storage device includes a plurality of storage cells. Each storage cell has a number of possible bit(s) directly corresponding to possible states of the storage cell. The memory access module further includes: a read only memory for storing a program code; and a microprocessor, coupled to the read only memory, for executing the program code to perform the following steps: performing a plurality of sensing operations, wherein a first sensing operation corresponds to a first sensing voltage, and each subsequent sensing operation corresponds to a sensing voltage determined according to a result of the previous sensing operation; using the plurality of sensing operations to generate a first digital value and a second digital value of a storage cell; using the first and the second digital value to obtain soft information of a same bit stored in the storage cell; and using the soft information to perform soft decoding.
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