公开(公告)号：US06444371B1

公开(公告)日：2002-09-03

申请号：US09377541

申请日：1999-08-19

申请人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

发明人： Syun-Ming Jang ,  Jui-Yu Chang ,  Chen-Hua Yu ,  Chung-Long Chang ,  Tsu Shih ,  Jeng-Horng Chen

IPC分类号： G03F900

CPC分类号： H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

摘要： Described is a novel method for the formation of topological features during the processing of a semiconductor wafer into integrated circuit devices. The present invention is most useful for those processes used to form advanced multilevel ultra-large scale integrated circuits where global planarization techniques, such as chemical mechanical polishing, is used. The present invention is applicable to all processes used to form modern high density, multilevel integrated circuits and without respect of the number of layers formed or materials used. In the present invention, a substrate is a semiconductor wafer or portion thereof, and is the material on which the described processes alter and the layers are formed.

摘要翻译： 描述了在将半导体晶片加工成集成电路器件期间形成拓扑特征的新颖方法。 本发明对于用于形成先进的多级超大规模集成电路的那些工艺是最有用的，其中使用诸如化学机械抛光的全局平面化技术。 本发明适用于用于形成现代高密度，多级集成电路的所有方法，并且不受所形成的层数或使用的材料的影响。 在本发明中，衬底是半导体晶片或其一部分，并且是所述工艺改变并形成层的材料。

公开(公告)号：US06362085B1

公开(公告)日：2002-03-26

申请号：US09619029

申请日：2000-07-19

申请人： Mo-Chiun Yu ,  Syun-Ming Jang ,  Chen-Hua Yu

发明人： Mo-Chiun Yu ,  Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： H01L214763

CPC分类号： H01L21/2822 ,  H01L21/26506 ,  H01L21/28202 ,  H01L21/28211 ,  H01L29/518

摘要： A process for forming a nitrogen enriched ultra thin gate oxide is described. The nitrogen enrichment increases the dielectric constant of the gate oxide thereby decreasing it's effective oxide thickness. This in turn enhances the performance of MOSFET devices formed thereon. The nitrogen enrichment is accomplished by first enriching the surface of a silicon wafer with nitrogen by implanting nitrogen atoms into the silicon through a sacrificial screen oxide. After fixing the nitrogen by annealing, a nitrogen enriched gate oxide is thermally grown. Additional nitrogen is then infused into the gate oxide by remote plasma nitridation. This two step nitrogen enrichment process increases the dielectric constant of the gate oxide by a significant amount, approaching that of silicon nitride which not only decreases it's effective thickness with respect to gate capacitance, but also lowers device leakage by suppressing hot carrier injection over device drain regions. In addition, because the initial silicon surface is nitrogen rich, the thermal oxidation rate is reduced. The reduction of oxidation rate improves process control by making the oxidation time and temperature more manageable. A further benefit nitrogen of enrichment of the gate oxide is improvement of the durability of the gate oxide when used as an etch stop during polysilicon gate patterning.

摘要翻译： 描述了形成富氮超薄栅极氧化物的方法。 氮富集增加了栅极氧化物的介电常数，从而降低了其有效的氧化物厚度。 这反过来又增强了在其上形成的MOSFET器件的性能。 氮富集通过首先通过将氮原子注入到硅中通过牺牲屏蔽氧化物而用氮富集硅晶片的表面来实现。 在通过退火固定氮气之后，热生长富氮栅极氧化物。 然后通过远程等离子体氮化将额外的氮气输入到栅极氧化物中。 这种两步氮富集工艺使栅极氧化物的介电常数增加了大量，接近氮化硅的介电常数，这不仅降低了栅极电容的有效厚度，而且通过抑制器件漏极上的热载流子注入来降低器件泄漏 地区。 另外，由于初始硅表面富含氮，所以热氧化速率降低。 氧化速率的降低通过使氧化时间和温度更易于管理来改善过程控制。 栅极氧化物富集氮的另一个优点是当在多晶硅栅极图案化期间用作蚀刻停止时，提高了栅极氧化物的耐久性。

公开(公告)号：US06277745B1

公开(公告)日：2001-08-21

申请号：US09221965

申请日：1998-12-28

申请人： Chung-Shi Liu ,  Shau-Lin Shue ,  Syun-Ming Jang ,  Chen-Hua Yu

发明人： Chung-Shi Liu ,  Shau-Lin Shue ,  Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： H01L2144

CPC分类号： H01L21/02071 ,  H01L21/321 ,  H01L21/32136 ,  H01L21/76841 ,  H01L21/7685 ,  H01L21/76852 ,  H01L21/76885

摘要： The present invention relates to a new structure and method for the passivation of copper electrical interconnects for the semiconductor industry. More particularly, the invention details a convenient method for completing the passivation of copper lines after they have been patterned by a dry etch process. The method includes the formation of a sandwich structure consisting of a bottom barrier layer, a copper layer and a top barrier layer. After the sandwich structure is patterned with a dry etch, for example, the resultant exposed copper sidewalls are then passivated by means of a barrier metal spacer process. The fully encapsulated copper lines are highly resistant to oxidation, which is an, otherwise, inherent problem associated with the lack of self passivation/exhibited by bare copper films.

摘要翻译： 本发明涉及用于半导体工业的铜电互连钝化的新结构和方法。 更具体地，本发明详细描述了在通过干蚀刻工艺对其进行图案化之后完成铜线钝化的方便方法。 该方法包括形成由底部阻挡层，铜层和顶部阻挡层组成的夹层结构。 在用干蚀刻图案化夹层结构之后，然后通过阻挡金属间隔物工艺钝化所得到的暴露的铜侧壁。 完全封装的铜线具有很高的抗氧化性，这是另一种与裸铜膜缺乏自钝化/显示相关的固有问题。

公开(公告)号：US6165898A

公开(公告)日：2000-12-26

申请号：US177187

申请日：1998-10-23

申请人： Syun-Ming Jang ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： H01L21/768 ,  H01L21/3065

CPC分类号： H01L21/76807 ,  H01L2221/1036

摘要： A method for forming a via through a dielectric layer within a microelectronics fabrication. There is first provided a substrate having a contact region formed therein. There is then formed upon the substrate and covering the contact region a blanket first dielectric layer formed of a first dielectric material which is not susceptible to etching with an oxygen containing plasma. There is then formed upon the blanket first dielectric layer a blanket second dielectric layer formed of a second dielectric material which is susceptible to etching within the oxygen containing plasma. There is then formed upon the blanket second dielectric layer a blanket hard mask layer formed from a hard mask material which is not susceptible to etching within the oxygen containing plasma. There is then formed upon the blanket hard mask layer a patterned first photoresist layer which leaves exposed a portion of the blanket hard mask layer greater than and completely overlapping an a real dimension of a via to be formed through the blanket first dielectric layer to access the contact layer. There is then etched while employing a first plasma etch method the blanket hard mask layer to form a patterned hard mask layer defining a first trench formed through the patterned hard mask layer. There is then etched while employing a second plasma etch method and at least the patterned hard mask layer the blanket second dielectric layer to form a patterned second dielectric layer having a second trench formed therethrough, where the second plasma etch method employs the oxygen containing plasma which preferably simultaneously strips the patterned first photoresist layer. There is then formed over at least the patterned second dielectric layer a patterned second photoresist layer which defines the location of the via to be formed through the blanket first dielectric layer. There is then etched while employing a third plasma etch method and the patterned second photoresist layer as a third etch mask layer the via through the blanket first dielectric layer.

公开(公告)号：US6020249A

公开(公告)日：2000-02-01

申请号：US891088

申请日：1997-07-10

申请人： Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

发明人： Tsu Shih ,  Jui-Yu Chang ,  Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： G03F9/00 ,  H01L23/544 ,  H01L23/48

CPC分类号： G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54466 ,  H01L2223/54493 ,  H01L2924/0002

摘要： A method for forming alignment marks are disclosed for performing photoalignment after chemical-mechanical polishing (CMP). A trench is first formed in a silicon substrate and then alignment marks are formed at the bottom of the trench. The aspect ratio of the trench is selected to be so low that the dishing of the CMP pad can be prevented from reaching into the trench to damage the alignment marks therein. A trench structure is also provided whereby the alignment marks can be protected from the abrasive action of the CMP. Steps subsequent to the CMP can therefore proceed unimpeded with the presence of undamaged alignment marks.

公开(公告)号：US5858623A

公开(公告)日：1999-01-12

申请号：US826712

申请日：1997-04-07

申请人： Chen-Hua Yu ,  Syun-Ming Jang ,  Tsung-Hou Li

发明人： Chen-Hua Yu ,  Syun-Ming Jang ,  Tsung-Hou Li

IPC分类号： G03F7/16 ,  G03F7/26 ,  H01L21/266 ,  G03F7/00

CPC分类号： G03F7/168 ,  G03F7/26 ,  H01L21/266

摘要： A method for forming a patterned photoresist layer. There is first provided a substrate. There is then formed over the substrate a blanket photoresist layer. The blanket photoresist layer is then implanted with a first ion beam to form an ion implanted blanket photoresist layer. The first ion beam employs a first ion having a first energy and a first dose sufficient such that an ion implanted patterned photoresist layer formed from the ion implanted blanket photoresist layer will not substantially outgas when the ion implanted patterned photoresist layer is exposed to a second beam. The ion implanted blanket photoresist layer is then patterned to form the ion implanted patterned photoresist layer. The method may be employed in selective high energy beam processing of the substrate. The method is particularly suited to selective high energy ion implant processing of semiconductor substrates employed within integrated circuit microelectronics fabrications.

摘要翻译： 一种形成图案化光致抗蚀剂层的方法。 首先提供基板。 然后在衬底上形成覆盖光致抗蚀剂层。 然后用第一离子束注入覆盖光致抗蚀剂层以形成离子注入的覆盖光致抗蚀剂层。 第一离子束使用具有足够的第一能量和第一剂量的第一离子，使得当离子注入的图案化光致抗蚀剂层暴露于第二光束时，由离子注入的覆盖光致抗蚀剂层形成的离子注入的图案化光致抗蚀剂层将基本上不会出现气体 。 然后将离子注入的覆盖光致抗蚀剂层图案化以形成离子注入的图案化光致抗蚀剂层。 该方法可用于衬底的选择性高能束处理。 该方法特别适用于在集成电路微电子器件制造中采用的半导体衬底的选择性高能离子注入处理。

公开(公告)号：US5700737A

公开(公告)日：1997-12-23

申请号：US606955

申请日：1996-02-26

申请人： Chen-Hua Yu ,  Syun-Ming Jang

发明人： Chen-Hua Yu ,  Syun-Ming Jang

IPC分类号： H01L21/027 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/465

CPC分类号： H01L21/76802 ,  H01L21/0276 ,  H01L21/32139 ,  H01L21/76877 ,  H01L21/76885

摘要： This invention provides a method for forming dense electrode patterns having a high aspect ratio in a conductor metal layer. The method uses silicon nitride deposited using plasma enhanced chemical vapor deposition, PECVD, as an etch stop mask to protect the conductor metal and anti reflection coating when etching the electrode patterns. The PECVD silicon nitride is also used a mask to eliminate pattern dependence when forming inter-metal dielectric layers. The PECVD silicon nitride is also used as an etch stop mask when forming vias in the inter-metal dielectric for electrical conduction between electrode pattern layers.

摘要翻译： 本发明提供一种在导体金属层中形成具有高纵横比的致密电极图案的方法。 该方法使用使用等离子体增强化学气相沉积（PECVD）沉积的氮化硅作为蚀刻停止掩模，以在蚀刻电极图案时保护导体金属和抗反射涂层。 当形成金属间介电层时，PECVD氮化硅也被用作掩模以消除图案依赖性。 当在金属间电介质中形成用于电极图案层之间的导电的通孔时，PECVD氮化硅也被用作蚀刻停止掩模。

公开(公告)号：USRE38914E1

公开(公告)日：2005-12-06

申请号：US10329863

申请日：2002-12-26

申请人： Syun-Ming Jang ,  Chen-Hua Yu

发明人： Syun-Ming Jang ,  Chen-Hua Yu

IPC分类号： H01L21/768 ,  H01L21/3065

CPC分类号： H01L21/76807 ,  H01L2221/1036

摘要： A method for forming a via through a dielectric layer within a microelectronics fabrication. There is first provided a substrate having a contact region formed therein. There is then formed upon the substrate and covering the contact region a blanket first dielectric layer formed of a first dielectric material which is not susceptible to etching with an oxygen containing plasma. There is then formed upon the blanket first dielectric layer a blanket second dielectric layer formed of a second dielectric material which is susceptible to etching within the oxygen containing plasma. There is then formed upon the blanket second dielectric layer a blanket hard mask layer formed from a hard mask material which is not susceptible to etching within the oxygen containing plasma. There is then formed upon the blanket hard mask layer a patterned first photoresist layer which leaves exposed a portion of the blanket hard mask layer greater than and completely overlapping an areal deminsion of a via to be formed through the blanket first dielectric layer to access the contact layer. There is then etched while employing a first plasma etch method the blanket hard mask layer to form a patterned hard mask layer defining a first trench formed through the patterned hard mask layer. There is then etched while employing a second plasma etch method and at least the patterned hard mask layer the blanket second dielectric layer to form a patterned second dielectric layer having a second trench formed therethrough, where the second plasma etch method employs the oxygen containing plasma which preferably simultaneously strips the patterned first photoresist layer. There is then formed over at least the patterned second dielectric layer a patterned second photoresist layer which defines the location of the via to be formed through the blanket first dielectric layer. There is then etched while employing a third plasma etch method and the patterned second photoresist layer as a third etch mask layer the via through the blanket first dielectric layer.

公开(公告)号：US06734101B1

公开(公告)日：2004-05-11

申请号：US09998787

申请日：2001-10-31

申请人： Tien-I Bao ,  Jeng Shwang-Ming ,  Syun-Ming Jang ,  Chen-Hua Yu ,  Kuen-Chyr Lee

发明人： Tien-I Bao ,  Jeng Shwang-Ming ,  Syun-Ming Jang ,  Chen-Hua Yu ,  Kuen-Chyr Lee

IPC分类号： H01L214763

CPC分类号： H01L21/76832 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76838

摘要： A new method of reducing copper hillocks in copper metallization is described. An opening is made through a dielectric layer overlying a substrate on a wafer. A copper layer is formed overlying the dielectric layer and completely filling the opening. The copper layer is polished back to leave the copper layer only within the opening. Copper hillocks are reduced by: coating an oxide layer over the copper layer and the dielectric layer, thereafter heating the wafer using NH3 plasma, and thereafter depositing a capping layer overlying the oxide layer wherein the time lapse between polishing back the copper layer and depositing the capping layer is less than one day (24 hours).

摘要翻译： 描述了一种在铜金属化中减少铜小丘的新方法。 通过覆盖晶片上的衬底的电介质层形成开口。 形成覆盖在电介质层上并完全填充开口的铜层。 铜层被抛光回去，仅在开口内留下铜层。 通过以下方式减少铜小丘：在氧化层和电介质层上涂覆氧化层，然后使用NH 3等离子体加热晶片，然后沉积覆盖氧化物层的覆盖层，其中抛光铜层和沉积 覆盖层不到一天（24小时）。

公开(公告)号：US06672941B1

公开(公告)日：2004-01-06

申请号：US09696087

申请日：2000-10-26

申请人： Chen-Hua Yu ,  Syun-Ming Jang

发明人： Chen-Hua Yu ,  Syun-Ming Jang

IPC分类号： B24B100

CPC分类号： B24B37/013 ,  B24B37/04 ,  B24B37/042 ,  B24B49/16 ,  H01L21/30625

摘要： A method to planarize the surface of a semiconductor substrate having shallow trench isolation (STI) reduces erosion of a silicon nitride planarization stop layer, reduces dishing of large areas of the shallow trench isolation, and prevents under polishing of the surface of the semiconductor substrate that will leave portions of the silicon dioxide that fills the shallow trenches covering the silicon nitride planarization stop exposed, is described. The method to planarize the surface of a semiconductor substrate having shallow trenches begins by chemical/mechanical planarization polishing at a first product of platen pressure and platen speed to planarize the semiconductor substrate. Polishing at a first product of platen pressure and platen speed will cause a high rate of material removal with low selectivity to increase production throughput. The silicon nitride stop layer will be examined to determine an end point exposure of the silicon nitride stop layer. When the end point exposure of the silicon nitride stop layer is reached, chemical/mechanical planarization polishing at a low product of platen pressure and platen speed is started to planarize the semiconductor substrate of slow over polish to control thickness of a trench oxide of the shallow trench isolation to reduce dishing and minimize erosion. The method further has the step of buffing the surface of the semiconductor substrate to remove any residue from the chemical/mechanical planarization polishing and to remove any microscratches from the surface of the semiconductor substrate.

摘要翻译： 平坦化具有浅沟槽隔离（STI）的半导体衬底的表面的方法减少了氮化硅平坦化停止层的侵蚀，减少了大面积浅沟槽隔离的凹陷，并且防止在半导体衬底的表面的抛光 将描述填充覆盖氮化硅平坦化止挡露出的浅沟槽的二氧化硅部分。 平面化具有浅沟槽的半导体衬底的表面的方法开始于在压板压力和压板速度的第一乘积上的化学/机械平面化抛光，以使半导体衬底平坦化。 在压板压力和压板速度的第一个产品上进行抛光将导致高选择性的材料去除率，从而提高生产量。 将检查氮化硅阻挡层以确定氮化硅阻挡层的端点暴露。 当达到氮化硅终止层的终点曝光时，开始以压板压力和压板速度的低乘积进行化学/机械平面化抛光，以平缓化缓慢过抛光的半导体衬底，以控制浅层的沟槽氧化物的厚度 沟槽隔离以减少凹陷和最小化侵蚀。 该方法还具有抛光半导体衬底的表面以从化学/机械平面化抛光中除去任何残余物并从半导体衬底的表面去除任何微细凹凸的步骤。