公开(公告)号：US09383403B2

公开(公告)日：2016-07-05

申请号：US13785284

申请日：2013-03-05

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel ,  Baher S. Haroun

IPC: G01R31/26 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/26 ,  G01R31/31723 ,  G01R31/318505 ,  G01R31/318577

Abstract: This disclosure describes a novel method and apparatus for testing TSVs within a semiconductor device. According to embodiments illustrated and described in the disclosure, a TSV may be tested by stimulating and measuring a response from a first end of a TSV while the second end of the TSV held at ground potential. Multiple TSVs within the semiconductor device may be tested in parallel to reduce the TSV testing time according to the disclosure.

Abstract translation: 本公开描述了一种用于测试半导体器件内的TSV的新颖方法和装置。 根据本公开中所示和描述的实施例，可以通过刺激和测量来自TSV的第一端的响应来测试TSV，同时TSV的第二端保持在地电位。 根据本公开，可以并行测试半导体器件内的多个TSV以减少TSV测试时间。

公开(公告)号：US09347992B2

公开(公告)日：2016-05-24

申请号：US14728580

申请日：2015-06-02

Applicant: Texas Instruments Incorporated

Inventor： Lee D. Whetsel ,  Baher S. Haroun ,  Brian J. Lasher ,  Anjali Vij

IPC: G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/31727 ,  G01R31/318555

Abstract: IEEE 1149.1 Test Access Ports (TAPs) may be utilized at both IC and intellectual property core design levels. TAPs serve as serial communication ports for accessing a variety of embedded circuitry within ICs and cores including; IEEE 1149.1 boundary scan circuitry, built in test circuitry, internal scan circuitry, IEEE 1149.4 mixed signal test circuitry, IEEE P5001 in-circuit emulation circuitry, and IEEE P1532 in-system programming circuitry. Selectable access to TAPs within ICs is desirable since in many instances being able to access only the desired TAP(s) leads to improvements in the way testing, emulation, and programming may be performed within an IC. A TAP linking module is described that allows TAPs embedded within an IC to be selectively accessed using 1149.1 instruction scan operations.

Abstract translation: IEEE 1149.1测试接入端口（TAP）可用于IC和知识产权核心设计级别。 TAP用作用于访问IC和核心内的各种嵌入式电路的串行通信端口，包括： IEEE 1149.1边界扫描电路，内置测试电路，内部扫描电路，IEEE 1149.4混合信号测试电路，IEEE P5001在线仿真电路和IEEE P1532系统编程电路。 可选择地访问IC内的TAP是理想的，因为在许多情况下，仅能够访问期望的TAP导致在IC内可以执行测试，仿真和编程的方式的改进。 描述了一种TAP链接模块，其允许使用1149.1指令扫描操作来选择性地访问嵌入在IC内的TAP。

公开(公告)号：US09325334B2

公开(公告)日：2016-04-26

申请号：US13916331

申请日：2013-06-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Phillip Michel Nadeau ,  Django Trombley ,  Baher S. Haroun ,  Srinath Mathur Ramaswamy

IPC: H03L7/26

CPC classification number: H03L7/26

Abstract: A frequency reference device that includes a frequency reference generation unit to generate a frequency reference signal based on an absorption line of a gas.

Abstract translation: 一种频率参考装置，包括频率参考产生单元，用于基于气体的吸收线产生频率参考信号。

公开(公告)号：US08994585B2

公开(公告)日：2015-03-31

申请号：US13658611

申请日：2012-10-23

Applicant: Texas Instruments Incorporated

Inventor： Brian P. Ginsburg ,  Srinath M. Ramaswamy ,  Vijay B. Rentala ,  Eunyoung Seok ,  Baher S. Haroun

IPC: G01S13/00 ,  G01S7/282 ,  G01S13/93

CPC classification number: G01S7/282 ,  G01S13/931

Abstract: A method is provided. A first edge on a first gating signal is generated, and a local oscillator and a shared clocking circuit with the first edge on the first gating signal. A second edge on a second gating signal is generated following the first edge on the first gating signal, and a receiver circuit is activated with the second edge on the second gating signal, where the receiver circuit includes a mixer. A transmit pulse following the first edge on the first gating signal is generated with the transmit pulse having a third edge. A switch that short circuits outputs of the mixer is then released following the later of the third edge of the transmit pulse and a delay.

Abstract translation: 提供了一种方法。 产生第一选通信号的第一边沿，以及本地振荡器和共享时钟电路，其中第一边沿在第一选通信号上。 在第一选通信号的第一边缘之后产生第二选通信号上的第二边缘，并且接收器电路在第二选通信号上的第二边沿被激活，其中接收器电路包括混频器。 在发射脉冲具有第三边缘的情况下，产生在第一选通信号上的第一边沿之后的发射脉冲。 然后在发射脉冲的第三个边沿稍后并且延迟之后释放混频器输出短路的开关。

公开(公告)号：US20140369520A1

公开(公告)日：2014-12-18

申请号：US13920302

申请日：2013-06-18

Applicant: Texas Instruments Incorporated

Inventor： David H. Elwart, II ,  Vikas Suma Vinay ,  Christopher M. Graves ,  Baher S. Haroun

IPC: H03F1/30 ,  H02H9/04

CPC classification number: H03F1/305 ,  H02H9/045 ,  H03F1/523 ,  H03F3/187 ,  H03F3/68 ,  H03F2200/441 ,  H03F2200/444 ,  H03F2200/555 ,  H03K17/6874 ,  H03K2217/0018

Abstract: Self-grounded circuitry (10) includes a signal channel conducting an output voltage (VOUT1). A charge pump (2) powered by a reference voltage (VDD) produces a control voltage (VCP). The control signal is at a low level if the reference voltage is low and is boosted to a high level if the reference voltage is high. A ground switch circuit (15) includes a depletion mode transistor (MP1) having a source coupled to the output voltage, a gate coupled to the control voltage, and a drain coupled to ground. The transistor includes a well region (4-1) and a parasitic substrate diode (D3-1). A negative voltage protection circuit (17-1) includes a depletion mode first protection transistor (MP3-1) having a drain coupled to the well region, a source coupled to a source of a depletion mode second protection transistor (MP4-1) having a drain coupled to the output voltage, the first and second protection transistors each having a gate coupled to the control voltage, and also includes a diode (MN1) coupled to charge the well region from the control voltage conductor to prevent distortion of the output voltage.

Abstract translation: 自接地电路（10）包括传导输出电压（VOUT1）的信号通道。 由参考电压（VDD）供电的电荷泵（2）产生控制电压（VCP）。 如果参考电压较低，则控制信号处于低电平，并且如果参考电压高，则其升压到高电平。 接地开关电路（15）包括具有耦合到输出电压的源极的耗尽型晶体管（MP1），耦合到控制电压的栅极和耦合到地的漏极。 晶体管包括阱区（4-1）和寄生衬底二极管（D3-1）。 负电压保护电路（17-1）包括具有耦合到阱区的漏极的耗尽型第一保护晶体管（MP3-1），耦合到耗尽型第二保护晶体管（MP4-1）的源极的源极， 耦合到输出电压的漏极，第一和第二保护晶体管各自具有耦合到控制电压的栅极，并且还包括耦合到从控制电压导体对阱区域充电的二极管（MN1），以防止输出电压的失真 。

公开(公告)号：US20140292354A1

公开(公告)日：2014-10-02

申请号：US13851484

申请日：2013-03-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Baher S. Haroun ,  Rajarshi Mukhopadhyay ,  Paul Merle Emerson

IPC: G01B7/14 ,  G11B20/18

CPC classification number: G01B7/14 ,  G01B7/023

Abstract: A capacitive sensor has at least first and second conductive areas so that a first capacitance is formed between the first conductive area and a surface, and a second capacitance is formed between the second conductive area and the surface, and the ratio of the first capacitance to the second capacitance has a predetermined value only when the sensor is at a predetermined distance from the surface.

Abstract translation: 电容传感器具有至少第一和第二导电区域，使得在第一导电区域和表面之间形成第一电容，并且在第二导电区域和表面之间形成第二电容，并且将第一电容与第 只有当传感器距离表面处于预定距离时，第二电容具有预定值。

公开(公告)号：US20140111366A1

公开(公告)日：2014-04-24

申请号：US13658611

申请日：2012-10-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Brian P. Ginsburg ,  Srinath M. Ramaswamy ,  Vijay B. Rentala ,  Eunyoung Seok ,  Baher S. Haroun

IPC: G01S13/00

CPC classification number: G01S7/282 ,  G01S13/931

Abstract: A method is provided. A first edge on a first gating signal is generated, and a local oscillator and a shared clocking circuit with the first edge on the first gating signal. A second edge on a second gating signal is generated following the first edge on the first gating signal, and a receiver circuit is activated with the second edge on the second gating signal, where the receiver circuit includes a mixer. A transmit pulse following the first edge on the first gating signal is generated with the transmit pulse having a third edge. A switch that short circuits outputs of the mixer is then released following the later of the third edge of the transmit pulse and a delay.

Abstract translation: 提供了一种方法。 产生第一选通信号的第一边沿，以及本地振荡器和共享时钟电路，其中第一边沿在第一选通信号上。 在第一选通信号的第一边缘之后产生第二选通信号上的第二边缘，并且接收器电路在第二选通信号上的第二边沿被激活，其中接收器电路包括混频器。 在发射脉冲具有第三边缘的情况下，产生在第一选通信号上的第一边沿之后的发射脉冲。 然后在发射脉冲的第三个边沿稍后并且延迟之后释放混频器输出短路的开关。

公开(公告)号：US11415643B2

公开(公告)日：2022-08-16

申请号：US16657281

申请日：2019-10-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Baher S. Haroun ,  Arup Polley ,  Srinath M. Ramaswamy

IPC: G01R33/07 ,  H01L43/04 ,  H01L43/06

Abstract: An amplifier includes a graphene Hall sensor (GHS). The GHS includes a graphene layer formed above a substrate, a dielectric structure formed above a channel portion of the graphene layer, and a conductive gate structure formed above at least a portion of the dielectric structure above the channel portion of the graphene layer for applying a gate voltage. The GHS also includes first and second conductive excitation contact structures coupled with corresponding first and second excitation portions of the graphene layer for applying at least one of the following to the channel portion of the graphene layer: a bias voltage; and a bias current. The GHS further includes first and second conductive sense contact structures coupled with corresponding first and second sense portions of the graphene layer. The amplifier also includes a current sense amplifier (CSA) coupled to the GHS. The CSA senses current output from the GHS.

公开(公告)号：US20220206044A1

公开(公告)日：2022-06-30

申请号：US17138977

申请日：2020-12-31

Applicant: Texas Instruments Incorporated

Inventor： Arup Polley ,  Srinath M. Ramaswamy ,  Baher S. Haroun

IPC: G01R15/20

Abstract: A system comprises first and second Hall-effect sensors and an amplifier. The first Hall-effect sensor has a first bias current direction parallel to a first direction, a pair of first bias input terminals spaced along the first direction, and a pair of first sense output terminals spaced along an orthogonal second direction. The second Hall-effect sensor has a second bias current direction parallel to the second direction, a pair of second bias input terminals spaced along the second direction, and a pair of second sense output terminals connected out of phase with the first sense terminals. The amplifier has a pair of amplifier input terminals coupled to the first and second sense terminals.

公开(公告)号：US11353519B1

公开(公告)日：2022-06-07

申请号：US17114589

申请日：2020-12-08

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Arup Polley ,  Srinath M. Ramaswamy ,  Jo Bito ,  Baher S. Haroun

IPC: G01R33/00 ,  G01R33/07

Abstract: A Hall sensor circuit includes a first Hall sensor, a second Hall sensor, a first preamplifier circuit, a second preamplifier circuit, a subtractor circuit, and a duty cycling circuit. The first preamplifier circuit includes an input and an output. The input is coupled to the first Hall sensor. The second preamplifier circuit includes a first input, a second input, and an output. The first input is coupled to the second Hall sensor. The subtractor circuit includes a first input coupled to the output of the first preamplifier circuit, a second input coupled to the output of the second preamplifier circuit, and an output coupled to the second input of the second preamplifier circuit. The duty cycling circuit is coupled to the second preamplifier circuit and the second Hall sensor.