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    Simultaneous LVDS I/O signaling method and apparatus
    71.
    发明授权
    Simultaneous LVDS I/O signaling method and apparatus 有权

    公开(公告)号：US09813065B2

    公开(公告)日：2017-11-07

    申请号：US15282345

    申请日：2016-09-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lee D. Whetsel

    IPC: H03K19/0175 ,  H04L25/02

    CPC classification number: H03K19/01759 ,  H04L25/0272

    Abstract: First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.

    SHADOW ACCESS PORT METHOD AND APPARATUS
    74.
    发明申请
    SHADOW ACCESS PORT METHOD AND APPARATUS 审中-公开

    公开(公告)号：US20170261553A1

    公开(公告)日：2017-09-14

    申请号：US15609950

    申请日：2017-05-31

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lee D. Whetsel

    IPC: G01R31/3177 ,  G01R31/3185

    CPC classification number: G01R31/3177 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318555

    Abstract: The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.

    FALLING CLOCK EDGE JTAG BUS ROUTERS
    77.
    发明申请
    FALLING CLOCK EDGE JTAG BUS ROUTERS 审中-公开

    公开(公告)号：US20170227606A1

    公开(公告)日：2017-08-10

    申请号：US15499362

    申请日：2017-04-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lee D. Whetsel

    IPC: G01R31/3185 ,  G01R31/3177

    CPC classification number: G01R31/318597 ,  G01R31/31723 ,  G01R31/3177 ,  G01R31/318552 ,  G01R31/318555 ,  G01R31/318558

    Abstract: A falling edge controller includes a controller having an inverted TCK (Test Clock) input, a TMS (Test Mode Select) input, a shift register control output, an update register control output, and a shift output; a shift register having a TDI (Test Data In) input, a shift register control input coupled to the shift register control output, address inputs, a select input, address and select outputs, and a TDO (Test Data Out) output; an update register having address and select inputs coupled to the address and select outputs, an update register control input coupled to the update register control output, address outputs coupled to the address inputs, and a select output coupled to the select input; and address circuitry having address inputs coupled to the address outputs, and having an enable output.

    DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS
    78.
    发明申请
    DUAL MODE TEST ACCESS PORT METHOD AND APPARATUS 审中-公开

    公开(公告)号：US20170227604A1

    公开(公告)日：2017-08-10

    申请号：US15499373

    申请日：2017-04-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lee D. Whetsel

    IPC: G01R31/3177 ,  G01R31/317 ,  G01R31/28

    CPC classification number: G01R31/3177 ,  G01R31/3172 ,  G01R31/318536 ,  G01R31/318555 ,  G01R31/318572 ,  G06F1/10

    Abstract: An integrated circuit has controller circuitry having coupled to a test clock and a test mode select inputs, and having state a register clock state output, a register capture state output, and a register update state output. Register circuitry has a test data in lead input, control inputs coupled to the state outputs of the controller circuitry, and a control output. Connection circuitry has a control input connected to the control output of the register circuitry and selectively couples one of a first serial data output of first scan circuitry and a second serial data output of second scan circuitry to a test data out lead. Selection circuitry has an input connected to the serial data input lead, an input connected to a test pattern source lead, a control input coupled to the scan circuitry control output leads, and an output connected to the scan input lead.

    Low power scan path cells with hold state multiplexer circuitry
    80.
    发明授权
    Low power scan path cells with hold state multiplexer circuitry 有权

    公开(公告)号：US09684033B2

    公开(公告)日：2017-06-20

    申请号：US15270746

    申请日：2016-09-20

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Lee D. Whetsel

    IPC: G01R31/317 ,  G01R31/3185 ,  G01R31/3177

    CPC classification number: G01R31/318536 ,  G01R31/31721 ,  G01R31/31723 ,  G01R31/3177 ,  G01R31/318575 ,  G01R31/318577

    Abstract: Scan architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure describes a method of adapting conventional scan architectures into a low power scan architecture. The low power scan architecture maintains the test time of conventional scan architectures, while requiring significantly less operational power than conventional scan architectures. The low power scan architecture is advantageous to IC/die manufacturers since it allows a larger number of circuits (such as DSP or CPU core circuits) embedded in an IC/die to be tested in parallel without consuming too much power within the IC/die. Since the low power scan architecture reduces test power consumption, it is possible to simultaneously test more die on a wafer than previously possible using conventional scan architectures. This allows wafer test times to be reduced which reduces the manufacturing cost of each die on the wafer.

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