公开(公告)号：US20190199378A1

公开(公告)日：2019-06-27

申请号：US16292693

申请日：2019-03-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mohamed Farouk Mansour ,  June Chul Roh ,  Srinath Hosur

IPC: H03M13/29 ,  H03M13/27

CPC classification number: H03M13/2957 ,  H03M13/09 ,  H03M13/1515 ,  H03M13/27 ,  H03M13/2966 ,  H03M13/618

Abstract: Disclosed embodiments include a device having a transmitter circuit that includes an input to receive data blocks that are part of a set of incoming data, a parity bit generator to append a number of parity bits to each of the received data blocks, a first encoder to apply a first type of encoding to create first coded blocks based on the received data blocks and the parity bits, an interleaver to interleave symbols in the first coded blocks to create additional blocks having a block size, wherein the number of parity bits appended to each of the received blocks is based on the block size, and a second encoder to apply a second type of encoding to create an output based on the additional blocks, wherein the second type of encoding is different from the first type of encoding.

公开(公告)号：US20180176052A1

公开(公告)日：2018-06-21

申请号：US15899310

申请日：2018-02-19

Applicant: Texas Instruments Incorporated

Inventor： Timothy Mark Schmidl ,  Srinath Hosur ,  Anuj Batra

IPC: H04L27/00 ,  H04L27/26

CPC classification number: H04L27/0012 ,  H04L27/2613

Abstract: A method of communicating in a wireless network including a plurality of nodes having communications devices including a first node, wherein at least one node utilizes a first physical layer (PHY) modulation, and at least one other node utilizes a second PHY modulation different from the first PHY modulation. The first node receives a PHY frame transmitted by one of the plurality of nodes, and identifies a PHY modulation type selected from the first PHY modulation and the second PHY modulation used in the PHY frame or to be used in a subsequently to be received PHY frame or frame portion. The first node decodes the PHY frame or the subsequently to be received PHY frame or frame portion using the PHY modulation type identified in the identifying step.

公开(公告)号：US09811136B2

公开(公告)日：2017-11-07

申请号：US15063001

申请日：2016-03-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Deric W. Waters ,  Srinath Hosur ,  Anand Dabak

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32

CPC classification number: G06F1/266 ,  G06F1/263 ,  G06F1/32

Abstract: A VBUS conductor is checked to determine whether a voltage on the VBUS conductor is greater than a vSafe0V voltage within a detect time interval. A device policy manager applies a vSafeDB voltage to the VBUS conductor when the voltage on the VBUS conductor is greater than the vSafe0V voltage. The policy engine waits for a bit stream to be detected within a timer interval. When the bit stream is not detected within the timer interval, the device policy manager is instructed to apply the vSafe0V voltage to the VBUS conductor. The device policy manager applies a vSafe5V voltage to the VBUS conductor when the bit stream is detected, and the policy engine waits for the bit stream to stop within a device ready timer interval. When the bit stream has stopped within the device ready timer interval, the policy engine sends capabilities as a source port.

公开(公告)号：US09699705B2

公开(公告)日：2017-07-04

申请号：US13901814

申请日：2013-05-24

Applicant: Texas Instruments Incorporated

Inventor： Nirmal Chindhu Warke ,  Srinath Hosur ,  Martin J. Izzard ,  Siraj Akhtar ,  Baher S. Haroun ,  Marco Corsi

IPC: H04W40/00 ,  H01Q3/26 ,  H01Q21/00 ,  H04L12/935 ,  H04L12/931 ,  H04W40/06 ,  H04W40/12

CPC classification number: H04W40/00 ,  H01Q3/26 ,  H01Q9/20 ,  H01Q21/0006 ,  H01Q21/0037 ,  H04B7/0617 ,  H04B17/336 ,  H04L45/74 ,  H04L49/3009 ,  H04L49/40 ,  H04W40/06 ,  H04W40/12 ,  Y02D70/00 ,  Y02D70/166 ,  Y02D70/322 ,  Y02D70/34

Abstract: Embodiments of the invention provide a system and method for chip to chip communications in electronic circuits. A router or switch receives data packets at input port ASICs. A routing table on the input port ASIC or on a routing ASIC is used to identify a destination port ASIC based upon header information in the data packet. The data packet is transmitted from the input port ASIC to the destination port ASIC using millimeter wave signals that are transmitted across a waveguide or a wireless interface.

公开(公告)号：US20170012617A1

公开(公告)日：2017-01-12

申请号：US15206014

申请日：2016-07-08

Applicant: Texas Instruments Incorporated

Inventor： Ariel Dario Moctezuma ,  Srinath Hosur

IPC: H03K17/082 ,  H02H3/26

CPC classification number: H03K17/0822 ,  H02H3/087 ,  H02H3/10 ,  H03K2217/0027

Abstract: In described examples, a switch has: a first current handling terminal coupled to a supply source terminal; and a second current handling terminal coupled to an output terminal. A comparator has: a first input coupled to the second current handling terminal; and a second input. A voltage reference source has: a first terminal coupled to the first current handling terminal; and a second terminal coupled to the second input of the comparator. A slew rate detector has an input coupled to the second current handling terminal. A switch controller has: a first input coupled to the comparator output; and a second input coupled to an output of the slew rate detector. The switch controller is coupled to output a signal to cause the switch to open when the comparator detects an over-current condition through the switch while the slew rate detector detects a negative slew rate.

Abstract translation: 在所述示例中，开关具有：耦合到电源端子的第一电流处理端子; 以及耦合到输出端子的第二电流处理终端。 比较器具有：耦合到第二电流处理终端的第一输入; 和第二个输入。 电压参考源具有：耦合到第一电流处理终端的第一端子; 以及耦合到比较器的第二输入端的第二端子。 转换速率检测器具有耦合到第二电流处理终端的输入。 开关控制器具有：耦合到比较器输出的第一输入; 以及耦合到转换速率检测器的输出的第二输入。 当转换速率检测器检测到负的压摆率时，比较器通过开关检测到过电流状态时，开关控制器被耦合以输出信号以使开关断开。

公开(公告)号：US09154350B2

公开(公告)日：2015-10-06

申请号：US14061429

申请日：2013-10-23

Applicant: Texas Instruments Incorporated

Inventor： Anuj Batra ,  Timothy M. Schmidl ,  Srinath Hosur ,  June C. Roh

IPC: H04B7/00 ,  H04L27/20 ,  H04L27/18 ,  H04W4/00 ,  H04L29/06

CPC classification number: H04W4/80 ,  H04L27/18 ,  H04L27/20 ,  H04L27/2675 ,  H04L69/22 ,  H04W52/36 ,  H04W52/367 ,  H04W72/0453 ,  H04W74/0816

Abstract: In at least some embodiments, a communication device includes a transceiver with a physical (PHY) layer. The PHY layer is configured for body area network (BAN) operations in a limited multipath environment using M-ary PSK, differential M-ary PSK or rotated differential M-ary PSK. Also, the PHY layer uses a constant symbol rate for BAN packet transmissions.

Abstract translation: 在至少一些实施例中，通信设备包括具有物理（PHY）层的收发器。 PHY层被配置为使用M-ary PSK，差分M-ary PSK或旋转差分M-ary PSK的有限多径环境中的身体局域网（BAN）操作。 此外，PHY层对于BAN分组传输使用恒定的符号率。

公开(公告)号：US09143187B2

公开(公告)日：2015-09-22

申请号：US14264708

申请日：2014-04-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： June Chul Roh ,  Anuj Batra ,  Sudipto Chakraborty ,  Srinath Hosur

IPC: H04B1/00 ,  H04B1/69 ,  H04B1/7176

CPC classification number: H04B1/69 ,  H04B1/7176 ,  H04B2001/6908

Abstract: A symbol modulation system applicable to a body area network is disclosed herein. The symbol modulation system includes a symbol mapper. The symbol mapper is configured to determine a time within a predetermined symbol transmission interval at which a transmission representative of the symbol will occur. The time is determined based on a value of a symbol and a value of a time-hopping sequence. The time is selected from a plurality of symbol value based time slots, and a plurality of time-hopping sequence sub-time-slots within each symbol value based time slot. The symbol mapper is configured to generate a single guard interval within the symbol transmission interval. The single guard interval is positioned to terminate the symbol transmission interval.

Abstract translation: 本文公开了适用于体区网络的符号调制系统。 符号调制系统包括符号映射器。 符号映射器被配置为确定符号的传输代表将发生的预定符号传输间隔内的时间。 该时间基于符号的值和跳时序列的值来确定。 该时间是从基于多个符号值的时隙中选出的，以及在每个基于符号值的时隙内的多个跳时序列子时隙。 符号映射器被配置为在符号传输间隔内产生单个保护间隔。 单个保护间隔定位成终止符号传输间隔。

公开(公告)号：US08966346B2

公开(公告)日：2015-02-24

申请号：US14073128

申请日：2013-11-06

Applicant: Texas Instruments Incorporated

Inventor： June Chul Roh ,  Anuj Batra ,  Srinath Hosur

IPC: H03M13/00 ,  H04L29/06 ,  H03M13/15 ,  H04L1/00 ,  H04L12/26 ,  H04L1/18

CPC classification number: H04L69/22 ,  H03M13/152 ,  H03M13/155 ,  H04L1/0057 ,  H04L1/0079 ,  H04L1/1812 ,  H04L43/0823

Abstract: Apparatus and method for processing a physical layer protocol convergence (PLCP) header. In one embodiment, a wireless device includes a PLCP header processor. The PLCP header processor is configured to: process a physical layer header, process a check value based on the physical layer header, and process an error correction code based on the physical layer header and the check value. A concatenation of the physical layer header, check value, and error correction code the PLCP header processor is configured to process consists of a number of information bits that is an integer multiple of a number of information bits per symbol used to encode the PLCP header.

Abstract translation: 用于处理物理层协议收敛（PLCP）报头的装置和方法。 在一个实施例中，无线设备包括PLCP头处理器。 PLCP头处理器被配置为：处理物理层报头，基于物理层报头处理检查值，并且基于物理层报头和检查值处理纠错码。 配置为处理的PLCP头处理器的物理层报头，检查值和纠错码的级联由多个信息位组成，每个信息位是用于编码PLCP报头的每个符号的信息位数的整数倍。

公开(公告)号：US20140112330A1

公开(公告)日：2014-04-24

申请号：US14025628

申请日：2013-09-12

Applicant: Texas Instruments Incorporated

Inventor： Timothy M. Schmidl ,  Anuj Batra ,  Srinath Hosur

IPC: H04W56/00 ,  H04W4/00

CPC classification number: H04W56/001 ,  H04L27/2613 ,  H04L27/2634 ,  H04W4/80

Abstract: A method includes receiving a first plurality of symbols comprising complex portions. The method further includes applying conjugate symmetry to the first plurality of symbols, producing a second plurality of symbols comprising no complex portions. The method further includes transforming the second plurality of symbols using an inverse fast Fourier transform, producing a third plurality of symbols. The method further includes interpolating the third plurality of symbols, generating a short training field comprising at least one real portion of the third plurality of symbols, generating a long training field comprising at least one real portion of the third plurality of symbols, and transmitting the short training field and long training field in a WPAN.

Abstract translation: 一种方法包括接收包括复数部分的第一多个符号。 该方法还包括将共轭对称性应用于第一多个符号，产生不包含复杂部分的第二多个符号。 该方法还包括使用快速傅里叶反变换来变换第二多个符号，产生第三个多个符号。 该方法还包括内插第三多个符号，产生包括第三多个符号的至少一个实部的短训练场，产生包括第三多个符号的至少一个实部的长训练场，并发送 短期培训领域和长期培训领域的WPAN。

公开(公告)号：US20140064336A1

公开(公告)日：2014-03-06

申请号：US14074448

申请日：2013-11-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： June Chul Roh ,  Anuj Batra ,  Sudipto Chakraborty ,  Srinath Hosur

IPC: H04B1/69

CPC classification number: H04B1/69 ,  H04B1/7176 ,  H04B2001/6908

Abstract: A symbol modulation system applicable to a body area network is disclosed herein. The symbol modulation system includes a symbol mapper. The symbol mapper is configured to determine a time within a predetermined symbol transmission interval at which a transmission representative of the symbol will occur. The time is determined based on a value of a symbol and a value of a time-hopping sequence. The time is selected from a plurality of symbol value based time slots, and a plurality of time-hopping sequence sub-time-slots within each symbol value based time slot. The symbol mapper is configured to generate a single guard interval within the symbol transmission interval. The single guard interval is positioned to terminate the symbol transmission interval.