公开(公告)号：US20210202735A1

公开(公告)日：2021-07-01

申请号：US17201673

申请日：2021-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Yun Peng ,  Fu-Ting Yen ,  Ting-Ting Chen ,  Keng-Chu Lin ,  Tsu-Hsiu Perng

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/66

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.

公开(公告)号：US20210193798A1

公开(公告)日：2021-06-24

申请号：US16937344

申请日：2020-07-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shuen-Shin Liang ,  Chen-Han Wang ,  Keng-Chu Lin ,  Tstsuji Ueno ,  Ting-Ting Chen

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/02

Abstract: The present disclosure relates to a semiconductor device including first and second terminals formed on a fin region and a seal layer formed between the first and second terminals. The seal layer includes a silicon carbide material doped with oxygen. The semiconductor device also includes an air gap surrounded by the seal layer, the fin region, and the first and second terminals.

公开(公告)号：US11018258B2

公开(公告)日：2021-05-25

申请号：US16716175

申请日：2019-12-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Yun Peng ,  Keng-Chu Lin

IPC: H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/308 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/8238

Abstract: A device includes a semiconductor fin and a shallow trench isolation (STI) structure. The semiconductor fin extends from a semiconductor substrate. The STI structure is around a lower portion of the semiconductor fin, and the STI structure includes a liner layer and an isolation material. The liner layer includes a metal-contained ternary dielectric material. The isolation material is over the liner layer.

公开(公告)号：US10522360B2

公开(公告)日：2019-12-31

申请号：US15730934

申请日：2017-10-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ya-Ling Lee ,  Shing-Chyang Pan ,  Keng-Chu Lin ,  Wen-Cheng Yang ,  Chih-Tsung Lee ,  Victor Y. Lu

IPC: H01L21/285 ,  H01L21/8234 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/768

Abstract: A method for forming a semiconductor device structure is provided. The method includes disposing a semiconductor substrate in a physical vapor deposition (PVD) chamber. The method also includes introducing a plasma-forming gas into the PVD chamber, and the plasma-forming gas contains an oxygen-containing gas. The method further includes applying a radio frequency (RF) power to a metal target in the PVD chamber to excite the plasma-forming gas to generate plasma. In addition, the method includes directing the plasma towards the metal target positioned in the PVD chamber such that an etch stop layer is formed over the semiconductor substrate.

公开(公告)号：US10510874B2

公开(公告)日：2019-12-17

申请号：US15883684

申请日：2018-01-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Keng-Chu Lin ,  Shi-Ning Ju

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234

Abstract: A semiconductor device is disclosed that includes a plurality of isolation regions. A fin is arranged between the plurality of isolation regions. One of the plurality of isolation regions includes a first atomic layer deposition (ALD) layer, a second ALD layer, a flowable chemical vapor deposition (FCVD) layer, and a third ALD layer. The first ALD layer includes a first trench. The second ALD layer is formed in the first trench of the first ALD layer. The FCVD layer is formed in the first trench of the first ALD layer and on the second ALD layer. The third ALD layer is formed on the FCVD layer.

公开(公告)号：US20150311158A1

公开(公告)日：2015-10-29

申请号：US14791571

申请日：2015-07-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Joung-Wei Liou ,  Han-Ti Hsiaw ,  Keng-Chu Lin

IPC: H01L23/532 ,  H01L23/522

CPC classification number: H01L23/5329 ,  H01L21/486 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Some embodiments of the present disclosure relate to an integrated circuit device. The integrated circuit device includes a semiconductor substrate, and an inter-level dielectric layer arranged over the semiconductor substrate. An etch-stop layer is arranged over the inter-level dielectric layer. The etch-stop layer comprises silicon oxide, silicon nitride, or silicon oxynitride, and has a density greater than or equal to 2.15 g/cm3.

Abstract translation: 本公开的一些实施例涉及集成电路装置。 集成电路器件包括半导体衬底和布置在半导体衬底上的级间介电层。 蚀刻停止层布置在层间电介质层之上。 蚀刻停止层包括氧化硅，氮化硅或氮氧化硅，并且具有大于或等于2.15g / cm 3的密度。

公开(公告)号：US09076845B2

公开(公告)日：2015-07-07

申请号：US14045054

申请日：2013-10-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Joung-Wei Liou ,  Han-Ti Hsiaw ,  Keng-Chu Lin

IPC: H01L21/20 ,  H01L21/36 ,  H01L21/768 ,  H01L23/538 ,  H01L21/48

CPC classification number: H01L23/5329 ,  H01L21/486 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of manufacturing an integrated circuit device includes forming an inter-level dielectric layer over a semiconductor substrate, forming a transformative layer over the inter-level dielectric layer, forming a protective layer over the transformative layer without allowing the transformative layer to undergo a substantive transformation, and after forming the protective layer, causing the transformative layer to undergo a volume-increasing transformation. The volume-increasing transformation produces a high density material that provides an effective etch stop.

Abstract translation: 一种制造集成电路器件的方法包括在半导体衬底上形成层间电介质层，在层间电介质层之上形成变换层，在变压层上形成保护层，而不使变形层经历实质的 变形后，形成保护层后，使变形层发生体积增大变换。 增加体积的变换产生提供有效蚀刻停止的高密度材料。

公开(公告)号：US12154822B2

公开(公告)日：2024-11-26

申请号：US18302428

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chin-Hsiang Lin ,  Keng-Chu Lin ,  Shwang-Ming Jeng ,  Teng-Chun Tsai ,  Tsu-Hsiu Perng ,  Fu-Ting Yen

IPC: H01L27/088 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/66 ,  H01L29/78

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

公开(公告)号：US20240371939A1

公开(公告)日：2024-11-07

申请号：US18771232

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Mrunal Abhijith Khaderbad ,  Dhanyakumar Mahaveer Sathaiya ,  Keng-Chu Lin ,  Tzer-Min Shen

IPC: H01L29/10 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a channel member including a first channel layer and a second channel layer over the first channel layer, and a gate structure over the channel member. The first channel layer includes silicon, germanium, a III-V semiconductor, or a II-VI semiconductor and the second channel layer includes a two-dimensional material.

公开(公告)号：US20240363704A1

公开(公告)日：2024-10-31

申请号：US18771503

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chia-Hung Chu ,  Tsungyu Hung ,  Hsu-Kai Chang ,  Ding-Kang Shih ,  Keng-Chu Lin ,  Pang-Yen Tsai ,  Sung-Li Wang ,  Shuen-Shin Liang

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/285 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28518 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device structure according to the present disclosure includes a source feature and a drain feature, at least one channel structure extending between the source feature and the drain feature, a gate structure wrapped around each of the at least one channel structure, a semiconductor layer over the gate structure, a dielectric layer over the semiconductor layer, a doped semiconductor feature extending through the semiconductor layer and the dielectric layer to be in contact with the source feature, a metal contact plug over the doped semiconductor feature, and a buried power rail disposed over the metal contact plug.