公开(公告)号：US11195926B2

公开(公告)日：2021-12-07

申请号：US16681102

申请日：2019-11-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  Yu-Lin Yang ,  I-Sheng Chen ,  Tzu-Chiang Chen

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/786

Abstract: A gate-all-around structure including a first transistor is provided. The first transistor includes a semiconductor substrate having a top surface, and a first nanostructure over the top surface of the semiconductor substrate and between a first source and a first drain. The first transistor also includes a first gate structure around the first nanostructure, and an inner spacer between the first gate structure and the first source, wherein an interface between the inner spacer and the first gate structure is non-flat. The first transistor includes an isolation layer between the top surface of the semiconductor substrate and the first source and the first drain.

公开(公告)号：US11183560B2

公开(公告)日：2021-11-23

申请号：US16681097

申请日：2019-11-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  I-Sheng Chen ,  Tzu-Chiang Chen ,  Shih-Syuan Huang ,  Hung-Li Chiang

IPC: H01L29/76 ,  H01L31/113 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L21/8234

Abstract: Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and first nanostructures and second nanostructures formed over the substrate. The semiconductor structure further includes a first source/drain structure formed adjacent to the first nanostructures and a second source/drain structure formed adjacent to the second nanostructures. The semiconductor structure further includes a first contact plug formed over the first source/drain structure and a second contact plug formed over the second source/drain structure. In addition, a bottom portion of the first contact plug is lower than a bottom portion of the first nanostructures, and a bottom portion of the second contact plug is higher than a top portion of the second nanostructures.

公开(公告)号：US11145676B1

公开(公告)日：2021-10-12

申请号：US16880998

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li Chiang ,  Chao-Ching Cheng ,  Chih-Sheng Chang ,  Tzu-Chiang Chen ,  Jin Cai

IPC: G11C11/22 ,  H01L27/11597 ,  H01L43/08 ,  G11C11/16

Abstract: A memory device includes a plurality of word lines, a plurality of bit lines, a plurality of source lines and a plurality of multi-level memory cells is introduced. Each of the multi-level memory cells is coupled to one of the word lines, one of the bit lines and one of the source lines. Each of the multi-level memory cells includes a ferroelectric storage element and a magneto-resistive storage element cascaded to the ferroelectric storage element. The ferroelectric storage element is configured to store a first bit of a multi-bit data. The magneto-resistive storage element is configured to store a second bit of the multi-bit data.

公开(公告)号：US20210265501A1

公开(公告)日：2021-08-26

申请号：US16932268

申请日：2020-07-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Tse Hung ,  Chao-Ching Cheng ,  Tse-An Chen ,  Hung-Li Chiang ,  Lain-Jong Li ,  Tzu-Chiang Chen

IPC: H01L29/78 ,  H01L21/306 ,  H01L21/28 ,  H01L21/02 ,  H01L29/06

Abstract: In an embodiment, a device includes: a dielectric fin on a substrate; a low-dimensional layer on the dielectric fin, the low-dimensional layer including a source/drain region and a channel region; a source/drain contact on the source/drain region; and a gate structure on the channel region adjacent the source/drain contact, the gate structure having a first width at a top of the gate structure, a second width at a middle of the gate structure, and a third width at a bottom of the gate structure, the second width being less than each of the first width and the third width.

公开(公告)号：US11038044B2

公开(公告)日：2021-06-15

申请号：US16585278

申请日：2019-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  Hung-Li Chiang ,  Tzu-Chiang Chen ,  I-Sheng Chen

IPC: H01L29/66 ,  H01L29/08 ,  H01L21/311 ,  H01L21/02 ,  H01L29/165 ,  H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L21/308 ,  H01L21/265 ,  H01L29/10

Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed over a bottom fin structure. A sacrificial gate structure having sidewall spacers is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is removed. The second semiconductor layers are laterally recessed. Dielectric inner spacers are formed on lateral ends of the recessed second semiconductor layers. The first semiconductor layers are laterally recessed. A source/drain epitaxial layer is formed to contact lateral ends of the recessed first semiconductor layer. The second semiconductor layers are removed thereby releasing the first semiconductor layers in a channel region. A gate structure is formed around the first semiconductor layers.

公开(公告)号：US20210134945A1

公开(公告)日：2021-05-06

申请号：US17120852

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Li CHIANG ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  I-Sheng Chen

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/088

Abstract: The structure of a semiconductor device with isolation structures between FET devices and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming a fin structure on a substrate and forming polysilicon gate structures with a first threshold voltage on first fin portions of the fin structure. The method further includes forming doped fin regions with dopants of a first type conductivity on second fin portions of the fin structure, doping at least one of the polysilicon gate structures with dopants of a second type conductivity to adjust the first threshold voltage to a greater second threshold voltage, and replacing at least two of the polysilicon gate structures adjacent to the at least one of the polysilicon gate structures with metal gate structures having a third threshold voltage less than the first and second threshold voltages

公开(公告)号：US20210091229A1

公开(公告)日：2021-03-25

申请号：US16578389

申请日：2019-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Cheng ,  Chun-Chieh Lu ,  Hung-Li Chiang ,  Tzu-Chiang Chen

IPC: H01L29/786 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a first poly-material pattern, a first conductive element, a first semiconductor layer, and a first gate structure. The first poly-material pattern is over and protrudes outward from the substrate, wherein the first poly-material pattern includes a first active portion and a first poly-material portion joined to the first active portion. The first conductive element is over the substrate, wherein the first conductive element includes the first poly-material portion and a first metallic conductive portion covering at least one of a top surface and a sidewall of the first poly-material portion. The first semiconductor layer is over the substrate and covers the first active portion of the first poly-material pattern and the first conductive element. The first gate structure is over the first semiconductor layer located within the first active portion.

公开(公告)号：US10727344B2

公开(公告)日：2020-07-28

申请号：US16049273

申请日：2018-07-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chao-Ching Cheng ,  Chih Chieh Yeh ,  Cheng-Hsien Wu ,  Hung-Li Chiang ,  Jung-Piao Chiu ,  Tzu-Chiang Chen ,  Tsung-Lin Lee ,  Yu-Lin Yang ,  I-Sheng Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/165

Abstract: A semiconductor device includes a fin field effect transistor (FinFET). The FinFET includes a channel disposed on a fin, a gate disposed over the channel and a source and drain. The channel includes at least two pairs of a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. The first semiconductor layer has a different lattice constant than the second semiconductor layer. A thickness of the first semiconductor layer is three to ten times a thickness of the second semiconductor layer at least in one pair.

公开(公告)号：US20200075716A1

公开(公告)日：2020-03-05

申请号：US16118143

申请日：2018-08-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Chung Wang ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Tung Ying Lee

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/775

Abstract: The current disclosure describes techniques for forming a low resistance junction between a source/drain region and a nanowire channel region in a gate-all-around FET device. A semiconductor structure includes a substrate, multiple separate semiconductor nanowire strips vertically stacked over the substrate, a semiconductor epitaxy region adjacent to and laterally contacting each of the multiple separate semiconductor nanowire strips, a gate structure at least partially over the multiple separate semiconductor nanowire strips, and a dielectric structure laterally positioned between the semiconductor epitaxy region and the gate structure. The first dielectric structure has a hat-shaped profile.

公开(公告)号：US20200052131A1

公开(公告)日：2020-02-13

申请号：US16598750

申请日：2019-10-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： I-Sheng Chen ,  Chao-Ching Cheng ,  Tzu-Chiang Chen ,  Carlos H. Diaz

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423

Abstract: A nanowire FET device includes a vertical stack of nanowire strips configured as the semiconductor body. One or more of the top nanowire strips are receded and are shorter than the rest of the nanowire strips stacked lower. Inner spacers are uniformly formed adjacent to the receded nanowire strips and the rest of the nanowire strips. Source/drain structures are formed outside the inner spacers and a gate structure is formed inside the inner spacers, which wraps around the nanowire strips.