公开(公告)号：US20230361123A1

公开(公告)日：2023-11-09

申请号：US18354844

申请日：2023-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Yun-Ting Chou ,  Chih-Han Lin ,  Jr-Jung Lin

IPC: H01L27/092 ,  H01L21/311 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/31111 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/0847 ,  H01L29/66545

Abstract: An embodiment device includes a first source/drain region over a semiconductor substrate and a dummy fin adjacent the first source/drain region. The dummy fin comprising: a first portion comprising a first film and a second portion over the first portion, wherein the second portion comprises: a second film; and a third film. The third film is between the first film and the second film, and the third film is made of a different material than the first film and the second film. A width of the second portion is less than a width of the first portion. The device further comprises a gate stack along sidewalls of the dummy fin.

公开(公告)号：US11670711B2

公开(公告)日：2023-06-06

申请号：US17107589

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jr-Jung Lin ,  Chih-Han Lin ,  Jin-Aun Ng ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L21/283 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L21/283 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/66545

Abstract: Embodiments relate to integrated circuit fabrication, and more particularly to a metal gate electrode. An exemplary structure for a semiconductor device comprises a substrate comprising a major surface; a first gate electrode on the major surface comprising a first layer of multi-layer material; a first dielectric material adjacent to one side of the first gate electrode; and a second dielectric material adjacent to the other 3 sides of the first gate electrode, wherein the first dielectric material and the second dielectric material collectively surround the first gate electrode.

公开(公告)号：US20230116545A1

公开(公告)日：2023-04-13

申请号：US18065184

申请日：2022-12-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/768 ,  H01L23/485 ,  H01L29/417 ,  H01L23/522 ,  H01L23/528 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first metal layer formed over a substrate and a dielectric layer formed over the first metal layer. The semiconductor device structure further includes an adhesion layer formed in the dielectric layer and over the first metal layer and a second metal layer formed in the dielectric layer. The second metal layer is electrically connected to the first metal layer, and a portion of the adhesion layer is formed between the second metal layer and the dielectric layer. The adhesion layer includes a first portion lining with a top portion of the second metal layer, and the first portion has an extending portion along a vertical direction.

公开(公告)号：US20220384617A1

公开(公告)日：2022-12-01

申请号：US17818647

申请日：2022-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Ping Chen ,  Kuei-Yu Kao ,  Shih-Yao Lin ,  Chih-Han Lin ,  Ming-Ching Chang ,  Chao-Cheng Chen

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/8238

Abstract: A device includes a fin protruding from a semiconductor substrate; a gate stack over and along a sidewall of the fin; a gate spacer along a sidewall of the gate stack and along the sidewall of the fin; an epitaxial source/drain region in the fin and adjacent the gate spacer; and a corner spacer between the gate stack and the gate spacer, wherein the corner spacer extends along the sidewall of the fin, wherein a first region between the gate stack and the sidewall of the fin is free of the corner spacer, wherein a second region between the gate stack and the gate spacer is free of the corner spacer.

公开(公告)号：US20220359721A1

公开(公告)日：2022-11-10

申请号：US17814756

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Han Lin

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/78 ,  H01L21/8234

Abstract: A method includes forming an active channel region, forming a dummy channel region, forming a first gate dielectric layer over the active channel region, forming a second gate dielectric layer over the dummy channel region, removing the second gate dielectric layer from the dummy channel region, forming a gate isolation region over and contacting the dummy channel region, and forming a first gate stack and a second gate stack. The first gate stack is on the active channel region. The gate isolation region separates the first gate stack from the second gate stack.

公开(公告)号：US11488858B2

公开(公告)日：2022-11-01

申请号：US16870389

申请日：2020-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Kuei-Yu Kao ,  Chen-Ping Chen ,  Chih-Han Lin

IPC: H01L21/768 ,  H01L21/3065 ,  H01L21/306

Abstract: A method includes etching a semiconductor substrate to form a trench, with the semiconductor substrate having a sidewall facing the trench, and depositing a first semiconductor layer extending into the trench. The first semiconductor layer includes a first bottom portion at a bottom of the trench, and a first sidewall portion on the sidewall of the semiconductor substrate. The first sidewall portion is removed to reveal the sidewall of the semiconductor substrate. The method further includes depositing a second semiconductor layer extending into the trench, with the second semiconductor layer having a second bottom portion over the first bottom portion, and a second sidewall portion contacting the sidewall of the semiconductor substrate. The second sidewall portion is removed to reveal the sidewall of the semiconductor substrate.

公开(公告)号：US11437287B2

公开(公告)日：2022-09-06

申请号：US16871514

申请日：2020-05-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Yao Lin ,  Chih-Han Lin ,  Shu-Uei Jang ,  Ya-Yi Tsai ,  Shu-Yuan Ku

IPC: H01L21/8238 ,  H01L21/28 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66

Abstract: A device includes a semiconductor substrate and a first gate stack over the semiconductor substrate, the first gate stack being between a first gate spacer and a second gate spacer. The device further includes a second gate stack over the semiconductor substrate between the first gate spacer and the second gate spacer and a dielectric material separating the first gate stack from the second gate stack. The dielectric material is at least partially between the first gate spacer and the second gate spacer, a first width of an upper portion of the dielectric material is greater than a second width of a lower portion of the dielectric material, and a third width of an upper portion of the first gate spacer is less than a fourth width of a lower portion of the first gate spacer.

公开(公告)号：US20220270928A1

公开(公告)日：2022-08-25

申请号：US17739899

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L21/308 ,  H01L27/092 ,  H01L29/10 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/423

Abstract: A method includes providing a substrate having a channel region, forming a gate stack layer over the channel region, forming a patterned hard mask over the gate stack layer, etching a top portion of the gate stack layer through openings in the patterned hard mask with a first etchant, etching a middle portion and a bottom portion of the gate stack layer with a second etchant that includes a passivating gas. A gate stack is formed with a passivation layer deposited on sidewalls of the gate stack. The method also includes etching the gate stack with a third etchant, thereby removing a bottom portion of the passivation layer and recessing a bottom portion of the gate stack.

公开(公告)号：US11328962B2

公开(公告)日：2022-05-10

申请号：US17099613

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chang-Yin Chen ,  Che-Cheng Chang ,  Chih-Han Lin

IPC: H01L29/49 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/51 ,  H01L21/308 ,  H01L27/092 ,  H01L29/10 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/423

Abstract: A method includes providing a structure having a substrate and a fin protruding from the substrate, forming a gate stack layer over the fin, and patterning the gate stack layer in forming a gate stack. The patterning of the gate stack layer simultaneously forms a passivation layer on sidewall surfaces of the gate stack. The method also includes removing a bottom portion of the passivation layer, thereby exposing a bottom portion of the gate stack, while a top portion of the passivation layer remains. The method further includes laterally etching the bottom portion of the gate stack, thereby shrinking a width of the bottom portion of the gate stack.

公开(公告)号：US11271086B2

公开(公告)日：2022-03-08

申请号：US16877317

申请日：2020-05-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chih-Han Lin ,  Shih-Chang Tsai ,  Wen-Shuo Hsieh ,  Te-Yung Liu

IPC: H01L29/49 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/04 ,  H01L27/088 ,  H01L29/786 ,  H01L51/52 ,  H01L27/12 ,  H01L29/78

Abstract: A semiconductor device includes plurality of fin structures extending in first direction on semiconductor substrate. Fin structure's lower portion is embedded in first insulating layer. First gate electrode and second gate electrode structures extend in second direction substantially perpendicular to first direction over of fin structures and first insulating layer. The first and second gate electrode structures are spaced apart and extend along line in same direction. First and second insulating sidewall spacers are arranged on opposing sides of first and second gate electrode structures. Each of first and second insulating sidewall spacers contiguously extend along second direction. A second insulating layer is in region between first and second gate electrode structures. The second insulating layer separates first and second gate electrode structures. A third insulating layer is in region between first and second gate electrode structures. The third insulating layer is formed of different material than second insulating layer.