公开(公告)号：US20210175341A1

公开(公告)日：2021-06-10

申请号：US17178006

申请日：2021-02-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/308 ,  H01L29/78 ,  H01L21/762

Abstract: FinFET patterning methods are disclosed for achieving fin width uniformity. An exemplary method includes forming a mandrel layer over a substrate. A first cut removes a portion of the mandrel layer, leaving a mandrel feature disposed directly adjacent to a dummy mandrel feature. The substrate is etched using the mandrel feature and the dummy mandrel feature as an etch mask, forming a dummy fin feature and an active fin feature separated by a first spacing along a first direction. A second cut removes a portion of the dummy fin feature and a portion of the active fin feature, forming dummy fins separated by a second spacing and active fins separated by the second spacing. The second spacing is along a second direction substantially perpendicular to the first direction. A third cut removes the dummy fins, forming fin openings, which are filled with a dielectric material to form dielectric fins.

公开(公告)号：US10985277B2

公开(公告)日：2021-04-20

申请号：US16859779

申请日：2020-04-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Kuan-Ting Pan ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/16 ,  H01L21/8234

Abstract: A method includes forming a first semiconductor layer over a substrate. A second semiconductor layer is formed over the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are etched to form a fin structure that extends from the substrate. The fin structure has a remaining portion of first semiconductor layer and a remaining portion of the second semiconductor layer atop the remaining portion of the first semiconductor layer. A capping layer is formed to wrap around three sides of the fin structure. At least a portion of the capping layer and at least a portion of the remaining portion of the second semiconductor layer in the fin structure are oxidized to form an oxide layer wrapping around three sides of the fin structure.

公开(公告)号：US10886269B2

公开(公告)日：2021-01-05

申请号：US16133795

申请日：2018-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Kuan-Ting Pan ,  Shi-Ning Ju ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/00 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/308

Abstract: A semiconductor device has a substrate, a first dielectric fin, and an isolation structure. The substrate has a first semiconductor fin. The first dielectric fin is disposed over the substrate and in contact with a first sidewall of the first semiconductor fin, in which a width of the first semiconductor fin is substantially equal to a width of the first dielectric fin. The isolation structure is in contact with the first semiconductor fin and the first dielectric fin, in which a top surface of the isolation structure is in a position lower than a top surface of the first semiconductor fin and a top surface of the first dielectric fin.

公开(公告)号：US10825919B2

公开(公告)日：2020-11-03

申请号：US16282214

申请日：2019-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsiung Lin ,  Pei-Hsun Wang ,  Chih-Hao Wang ,  Kuo-Cheng Ching ,  Jui-Chien Huang

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06

Abstract: A method of fabricating semiconductor devices is provided. The method includes forming a fin structure on a substrate, in which the fin structure includes a fin stack of alternating first and second semiconductor layers and forming recesses in the fin stack at source and drain regions. The method also includes etching the second semiconductor layers to form recessed second semiconductor layers, and forming third semiconductor layers on sidewalls of the recessed second semiconductor layers. The method further includes epitaxially growing source and drain structures in the recesses, removing the recessed second semiconductor layers to form spaces between the first semiconductor layers, and oxidizing the third semiconductor layers to form inner spacers. In addition, the method includes forming a gate structure to fill the spaces and to surround the first semiconductor layers.

公开(公告)号：US10763365B2

公开(公告)日：2020-09-01

申请号：US16176072

申请日：2018-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Liang Chen ,  Chih-Ming Lai ,  Ching-Wei Tsai ,  Charles Chew-Yuen Young ,  Jiann-Tyng Tzeng ,  Kuo-Cheng Ching ,  Ru-Gun Liu ,  Wei-Hao Wu ,  Yi-Hsiung Lin ,  Chia-Hao Chang ,  Lei-Chun Chou

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/528 ,  H01L27/088 ,  H01L29/66 ,  H01L23/535 ,  H01L21/8234 ,  H01L23/48 ,  H01L29/417

Abstract: The present disclosure describes various non-planar semiconductor devices, such as fin field-effect transistors (finFETs) to provide an example, having one or more metal rail conductors and various methods for fabricating these non-planar semiconductor devices. In some situations, the one or more metal rail conductors can be electrically connected to gate, source, and/or drain regions of these various non-planar semiconductor devices. In these situations, the one or more metal rail conductors can be utilized to electrically connect the gate, the source, and/or the drain regions of various non-planar semiconductor devices to other gate, source, and/or drain regions of various non-planar semiconductor devices and/or other semiconductor devices. However, in other situations, the one or more metal rail conductors can be isolated from the gate, the source, and/or the drain regions these various non-planar semiconductor devices. This isolation prevents electrical connection between the one or more metal rail conductors and the gate, the source, and/or the drain regions these various non-planar semiconductor devices.

公开(公告)号：US10741672B2

公开(公告)日：2020-08-11

申请号：US16204849

申请日：2018-11-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/45 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/28 ,  H01L29/423 ,  H01L21/3213 ,  H01L21/321

Abstract: A method of forming a fin field effect transistors (finFET) on a substrate includes forming a fin structure on the substrate, forming a protective layer on the fin structure, and forming a polysilicon structure on the protective layer. The method further includes modifying the polysilicon structure such that a first horizontal dimension of a first portion of the modified polysilicon structure is smaller than a second horizontal dimension of a second portion of the modified polysilicon structure. The method further includes replacing the modified polysilicon structure with a gate structure having a first horizontal dimension of a first portion of the gate structure that is smaller than a second horizontal dimension of a second portion of the gate structure.

公开(公告)号：US10700183B2

公开(公告)日：2020-06-30

申请号：US16226827

申请日：2018-12-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Kuan-Ting Pan ,  Shi-Ning Ju ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L21/762

Abstract: A method for forming a FinFET device structure includes forming a first fin structure in a core region of a substrate and a second fin structure in an input/output region of the substrate with a fin top layer and a hard mask layer over the fin structures. The method also includes forming a dummy oxide layer across the fin structures. The method also includes forming a dummy gate structure over the dummy oxide layer. The method also includes removing the dummy gate structure over fin structures. The method also includes removing the dummy oxide layer and trimming the fin structures. The method also includes forming first and second oxide layers across the first and second fin structures. The method also includes forming first and second gate structures over the first and second oxide layers across the first and second fin structures.

公开(公告)号：US10672892B2

公开(公告)日：2020-06-02

申请号：US16504829

申请日：2019-07-08

Applicant: Taiwan Semiconductor Manufacturing, Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Kuan-Lun Cheng

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/02 ,  H01L29/165 ,  H01L29/417 ,  H01L29/161 ,  H01L29/78

Abstract: Semiconductor structures including active fin structures, dummy fin structures, epitaxy layers, a Ge containing oxide layer and methods of manufacture thereof are described. By implementing the Ge containing oxide layer on the surface of the epitaxy layers formed on the source/drain regions of some of the FinFET devices, a self-aligned epitaxy process is enabled. By implementing dummy fin structures and a self-aligned etch, both the epitaxy layers and metal gate structures from adjacent FinFET devices are isolated in a self-aligned manner.

公开(公告)号：US10651171B2

公开(公告)日：2020-05-12

申请号：US15379632

申请日：2016-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Ying-Keung Leung ,  Chi On Chui

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/32 ,  H01L21/3105

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure on a substrate; a first gate stack and a second gate stack formed on the fin structure; a dielectric material layer disposed on the first and second gate stacks, wherein the dielectric layer includes a first portion disposed on a sidewall of the first gate stack with a first thickness and a second portion disposed on a sidewall of the second gate stack with a second thickness greater than the first thickness; a first gate spacer disposed on the first portion of the dielectric material layer; and a second gate spacer disposed on the second portion of the dielectric material layer.

公开(公告)号：US20200091312A1

公开(公告)日：2020-03-19

申请号：US16686475

申请日：2019-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/08

Abstract: A method includes receiving a substrate; forming on the substrate a semiconductor fin; an isolation structure surrounding the semiconductor fin; and first and second dielectric fins above the isolation structure and sandwiching the semiconductor fin; depositing a spacer feature filling spaces between the semiconductor fin and the first and second dielectric fins; performing an etching process to recess the semiconductor fin, resulting in a trench between portions of the spacer feature; and epitaxially growing a semiconductor material in the trench.