公开(公告)号：US06985038B2

公开(公告)日：2006-01-10

申请号：US10830450

申请日：2004-04-23

申请人： Toshitsugu Miwa ,  Takahiro Miki

发明人： Toshitsugu Miwa ,  Takahiro Miki

IPC分类号： H03F3/45

CPC分类号： H03F3/45937 ,  H03F3/45183 ,  H03F3/45641

摘要： A voltage setting circuit includes a voltage setting region setting a voltage level corresponding to a maximum value in amplitude of a signal output from an OTA circuit, a voltage setting region setting a voltage level corresponding to a minimum value in amplitude of the signal, and an intermediate voltage setting region setting a voltage intermediate between the voltages set by the above two regions. This intermediate voltage is input to a common mode feedback circuit and in accordance with the intermediate voltage the common mode feedback circuit generates a common mode voltage fed back to the OTA circuit.

摘要翻译： 电压设定电路包括电压设定区域，设定与从OTA电路输出的信号的振幅的最大值对应的电压电平，设定与信号幅度的最小值对应的电压电平的电压设定区域，以及 中间电压设定区域设定由上述两个区域设定的电压之间的电压。 该中间电压被输入到共模反馈电路，并且根据中间电压，共模反馈电路产生反馈到OTA电路的共模电压。

公开(公告)号：US06798678B2

公开(公告)日：2004-09-28

申请号：US09900017

申请日：2001-07-09

申请人： Hiroshi Komurasaki ,  Hisayasu Sato ,  Takahiro Miki

发明人： Hiroshi Komurasaki ,  Hisayasu Sato ,  Takahiro Miki

IPC分类号： H02M500

CPC分类号： H03L7/0805 ,  H03D3/06 ,  H03K5/135 ,  H03K9/06 ,  H03L7/0812 ,  H03L7/0995 ,  H04L27/14

摘要： There is provided a frequency voltage converter comprises a first transmission line for transmitting an input signal and a second transmission line provided with a delay line circuit, a third transmission line for transmitting a reference signal and a fourth transmission line provided with a delay line circuit, a mixer circuit, and a locked loop having a control circuit for outputting the same control signal to control portions of both delay line circuits so that the amount of a delay by the delay line circuit reaches one cycle of the reference signal, thereby holding linearity with respect to the frequency of a modulated wave signal and executing frequency voltage conversion even when a center frequency is low.

摘要翻译： 提供了一种频率电压转换器，包括用于发送输入信号的第一传输线和设置有延迟线电路的第二传输线，用于传送参考信号的第三传输线和设置有延迟线电路的第四传输线， 混频器电路和锁定环路，具有控制电路，用于将相同的控制信号输出到两个延迟线电路的控制部分，使得延迟线电路的延迟量达到参考信号的一个周期，从而保持与 相对于调制波信号的频率，即使中心频率低，也执行频率电压转换。

公开(公告)号：US5633611A

公开(公告)日：1997-05-27

申请号：US557713

申请日：1995-11-13

申请人： Hiroyuki Kohno ,  Takahiro Miki

发明人： Hiroyuki Kohno ,  Takahiro Miki

IPC分类号： G05F3/24 ,  H03K17/16 ,  H03K17/687 ,  H03K17/693 ,  H03K19/0185 ,  H03M1/74

CPC分类号： H03K19/018578 ,  G05F3/24 ,  H03K17/693

摘要： Driving circuits (6) output driving signals to drive switching transistors (Q 15, Q16). A potential as the high level of the driving signal can be set lower than a power supply voltage (V.sub.DD) by connecting the sources of transistors (Q18, Q20) to a node (X). This configuration prevents an overshoot at a switching time and allows an improvement in a settling time. Therefore, a complementary current source circuit for a high-speed D/A converter can be provided.

摘要翻译： 驱动电路（6）输出驱动信号以驱动开关晶体管（Q15，Q16）。 通过将晶体管（Q18，Q20）的源极连接到节点（X），驱动信号的高电平的电位可以设定为低于电源电压（VDD）。 该配置防止在切换时间的过冲，并且可以提高建立时间。 因此，可以提供用于高速D / A转换器的互补电流源电路。

公开(公告)号：US5517152A

公开(公告)日：1996-05-14

申请号：US948355

申请日：1992-09-23

申请人： Takahiro Miki ,  Yasuyuki Nakamura ,  Shiro Hosotani

发明人： Takahiro Miki ,  Yasuyuki Nakamura ,  Shiro Hosotani

IPC分类号： G05F3/24 ,  H02J1/00 ,  H03F3/343 ,  H03F3/345 ,  H03F3/347 ,  H03K3/356 ,  H03K17/041 ,  H03M1/74 ,  H01J19/82 ,  G05F1/10 ,  G05F3/04 ,  H03K3/00

CPC分类号： G05F3/242 ,  H03K17/04106 ,  H03K3/356017 ,  H03M1/745

摘要： A current source circuit according to the present invention is provided with an output terminal 100, a bias voltage source 21, N channel MOS transistors 2 and 1 and P channel MOS transistor 3. The source of transistor 2, the drain of transistor 1 and the drain of transistor 3 are connected to a common node, the drain of transistor 2 is connected to output terminal 100 and the gate of transistor 2 is connected to bias voltage source 21. Conductions of transistors 1 and 3 are dynamically controlled in response to an external signal. As a result, it is possible to implement a current source circuit having a small number of devices and enabling an operation at a high speed.

摘要翻译： 根据本发明的电流源电路设置有输出端子100，偏置电压源21，N沟道MOS晶体管2和1以及P沟道MOS晶体管3.晶体管2的源极，晶体管1的漏极和 晶体管3的漏极连接到公共节点，晶体管2的漏极连接到输出端子100，晶体管2的栅极连接到偏置电压源21.晶体管1和3的结合是响应于外部的 信号。 结果，可以实现具有少量器件的电流源电路，并且能够高速地进行操作。

公开(公告)号：US5315301A

公开(公告)日：1994-05-24

申请号：US976056

申请日：1992-11-13

申请人： Shiro Hosotani ,  Takahiro Miki ,  Masao Ito

发明人： Shiro Hosotani ,  Takahiro Miki ,  Masao Ito

IPC分类号： H03M1/08 ,  H03M1/06 ,  H03M1/36

CPC分类号： H03M1/0643 ,  H03M1/068 ,  H03M1/361

摘要： An improved parallel-type A/D converter is disclosed, which includes encoder 3 constituted by a pseudo-NMOS type ROM, and encoder 28 constituted by a pseudo-PMOS type ROM. These encoders are connected to the outputs of pre-encoder 2. Averaging circuit 29 receives binary data provided from two encoders to provide average value data of these as converted binary output data. Even in case of multi-addressing, an averaging circuit can provide correct data as converted data. As a result, an A/D converter which is not affected by noise or the like has been obtained.

摘要翻译： 公开了一种改进的并行型A / D转换器，其包括由伪NMOS型ROM构成的编码器3和由伪PMOS型ROM构成的编码器28。 这些编码器连接到预编码器2的输出。平均电路29接收从两个编码器提供的二进制数据，以将它们的平均值数据提供为转换的二进制输出数据。 即使在多寻址的情况下，平均电路也可以提供作为转换数据的正确数据。 结果，已经获得了不受噪声等影响的A / D转换器。

公开(公告)号：US4695826A

公开(公告)日：1987-09-22

申请号：US848562

申请日：1986-04-07

申请人： Hideki Ando ,  Takahiro Miki

发明人： Hideki Ando ,  Takahiro Miki

IPC分类号： H03M1/74 ,  H03M1/00 ,  H03M1/66

CPC分类号： H03M1/742

摘要： A digital-to-analog converter includes a plurality of constant current sources (401-407) arrayed in a prescribed order and connected with a grounding lead wire (70). The respective constant current sources (401-407) are selectively connected to a first bus (303) by corresponding switches (501-507), respectively. A decoder (2) outputs switching signals to the switches (501-507). The switching signals are outputted from the decoder (2) to the switches (501-507) so that the constant current sources symmetrically positioned with respect to the center of an array of the plurality of constant current sources (401-407) are sequentially connected to the first bus (303). Thus, the digital-to-analog converter is improved in linearity.

摘要翻译： 数模转换器包括以规定顺序排列并与接地引线（70）连接的多个恒流源（401-407）。 相应的恒定电流源（401-407）分别通过相应的开关（501-507）选择性地连接到第一总线（303）。 解码器（2）向开关（501-507）输出开关信号。 切换信号从解码器（2）输出到开关（501-507），使得相对于多个恒定电流源（401-407）的阵列的中心对称定位的恒流源顺序地连接 到第一巴士（303）。 因此，数模转换器的线性度得到改善。