公开(公告)号：US06826393B1

公开(公告)日：2004-11-30

申请号：US09547920

申请日：2000-04-11

申请人： Hiroshi Komurasaki ,  Hisayasu Sato ,  Takahiro Miki

发明人： Hiroshi Komurasaki ,  Hisayasu Sato ,  Takahiro Miki

IPC分类号： H04B128

CPC分类号： H03D7/1433 ,  H03D7/1425 ,  H03D7/1458 ,  H03D7/1491 ,  H03D2200/0025 ,  H03D2200/0043

摘要： A mixer circuit according to the present invention includes a first differential transistor pair of two transistors, a second differential transistor pair of two transistors, an impedance element connected to the first differential transistor pair, an impedance element connected to the second differential transistor pair, an inductor connected to nodes A, B, a current source connected to node A, a current source connected to node B, and a capacitor. A mixer circuit with high conversion gain and small distortion can be obtained.

摘要翻译： 根据本发明的混频器电路包括两个晶体管的第一差分晶体管对，两个晶体管的第二差分晶体管对，连接到第一差分晶体管对的阻抗元件，连接到第二差分晶体管对的阻抗元件， 电感器连接到节点A，B，连接到节点A的电流源，连接到节点B的电流源和电容器。 可以获得具有高转换增益和小失真的混频器电路。

公开(公告)号：US06798678B2

公开(公告)日：2004-09-28

申请号：US09900017

申请日：2001-07-09

申请人： Hiroshi Komurasaki ,  Hisayasu Sato ,  Takahiro Miki

发明人： Hiroshi Komurasaki ,  Hisayasu Sato ,  Takahiro Miki

IPC分类号： H02M500

CPC分类号： H03L7/0805 ,  H03D3/06 ,  H03K5/135 ,  H03K9/06 ,  H03L7/0812 ,  H03L7/0995 ,  H04L27/14

摘要： There is provided a frequency voltage converter comprises a first transmission line for transmitting an input signal and a second transmission line provided with a delay line circuit, a third transmission line for transmitting a reference signal and a fourth transmission line provided with a delay line circuit, a mixer circuit, and a locked loop having a control circuit for outputting the same control signal to control portions of both delay line circuits so that the amount of a delay by the delay line circuit reaches one cycle of the reference signal, thereby holding linearity with respect to the frequency of a modulated wave signal and executing frequency voltage conversion even when a center frequency is low.

摘要翻译： 提供了一种频率电压转换器，包括用于发送输入信号的第一传输线和设置有延迟线电路的第二传输线，用于传送参考信号的第三传输线和设置有延迟线电路的第四传输线， 混频器电路和锁定环路，具有控制电路，用于将相同的控制信号输出到两个延迟线电路的控制部分，使得延迟线电路的延迟量达到参考信号的一个周期，从而保持与 相对于调制波信号的频率，即使中心频率低，也执行频率电压转换。

公开(公告)号：US06069579A

公开(公告)日：2000-05-30

申请号：US131238

申请日：1998-08-07

申请人： Masao Ito ,  Takeshi Shigenobu ,  Toshio Kumamoto ,  Takahiro Miki ,  Hiroshi Komurasaki

发明人： Masao Ito ,  Takeshi Shigenobu ,  Toshio Kumamoto ,  Takahiro Miki ,  Hiroshi Komurasaki

IPC分类号： H03M1/14 ,  H03M1/20 ,  H03M1/36 ,  H03M1/12

CPC分类号： H03M1/205 ,  H03M1/141

摘要： An A/D converter simplifies its circuit configuration without deteriorating accuracy in A/D conversion. A circuit is formed of a folding and interpolation type. A gain-variable pre-amplifier group 11 amplifies each of reference voltages Vref1 to VrefN and an analog input voltage Vin, to output the result to a folding amplifier group 12, while a gain-variable pre-amplifier group 21 amplifies each of reference voltages Vrr1 to VrrJ and the analog input voltage Vin, to output the result to a comparator group 24. Each of pre-amplifiers constituting the gain-variable pre-amplifier groups 11 and 21 has an amplification factor that varies in upper and lower comparison periods according to a clock control signal .PHI.cnt.

摘要翻译： A / D转换器简化了其电路配置，而不会降低A / D转换的精度。 电路由折叠和内插形式组成。 增益可变前置放大器组11放大每个参考电压Vref1至VrefN和模拟输入电压Vin，以将结果输出到折叠放大器组12，而增益可变的前置放大器组21放大每个参考电压 Vrr1至VrrJ和模拟输入电压Vin，将结果输出到比较器组24.构成增益可变前置放大器组11和21的每个前置放大器具有在上和下比较周期内变化的放大系数， 到时钟控制信号PHI cnt。

公开(公告)号：US09564805B2

公开(公告)日：2017-02-07

申请号：US14009715

申请日：2012-04-09

申请人： Shinya Sano ,  Masashi Horiguchi ,  Takahiro Miki ,  Mitsuru Hiraki

发明人： Shinya Sano ,  Masashi Horiguchi ,  Takahiro Miki ,  Mitsuru Hiraki

IPC分类号： H02M3/158 ,  G05F3/30 ,  G05F3/26

CPC分类号： G05F3/267 ,  G05F3/20 ,  G05F3/26 ,  G05F3/30 ,  H02M3/158

摘要： A voltage generating circuit, in which the influence of offset of an amplifier on an output voltage is reduced, has first and second bipolar transistors (Q1, Q2) having emitter terminals at the same electric potential. A base terminal of Q1 is disposed on a collector side of Q2. A first resistance element connects the collector side of Q2 with the base side of Q2; and a second resistance element (R1) connects a collector side of Q1 to R2. A third resistance element (R3) connects a base terminal of Q2 with the electric potential of the emitter terminals. An amplifier (A1) outputs a voltage based on a voltage difference between the collector sides of Q1 and Q2; and a voltage-current converting section (MP1, MP2) converts amplifier output into a current supplied to the connection node of R1 and R2. A voltage is then output on the basis of the generated current.

摘要翻译： 其中放大器的偏移对输出电压的影响减小的电压产生电路具有在相同电位的发射极端子的第一和第二双极晶体管（Q1，Q2）。 Q1的基极端子设置在Q2的集电极侧。 第一电阻元件将Q2的集电极侧与Q2的基极侧连接; 并且第二电阻元件（R1）将Q1的集电极侧连接到R2。 第三电阻元件（R3）将Q2的基极端子与发射极端子的电位相连。 放大器（A1）输出基于Q1和Q2的集电极侧之间的电压差的电压; 电压电流转换部（MP1，MP2）将放大器输出转换为R1和R2的连接节点的电流。 然后基于所产生的电流输出电压。

公开(公告)号：US07295067B2

公开(公告)日：2007-11-13

申请号：US11181891

申请日：2005-07-15

申请人： Masaomi Kamakura ,  Takahiro Miki

发明人： Masaomi Kamakura ,  Takahiro Miki

IPC分类号： H03F3/45

CPC分类号： H03F3/45183 ,  H03F2203/45644

摘要： A current source block and a negative resistance generation block are connected in parallel. The negative resistance generation block generates a negative resistance in response to the minute variations of an output voltage. Thus the output resistance of a current source circuit is given by the combined resistance of the negative resistance and the resistance of a resistor in the current source block connected in parallel. The resistance of the resistor in the current source block and the negative resistance are controlled to be substantially the same to thereby increase the output resistance of the current source circuit. The current source circuit serves to increase an output resistance when viewed from an differential output terminal. As a result, use of this current source circuit realizes a differential amplifier providing a high gain.

摘要翻译： 电流源块和负电阻生成块并联连接。 负电阻产生块响应于输出电压的微小变化而产生负电阻。 因此，电流源电路的输出电阻由负电阻的组合电阻和并联连接的电流源模块中的电阻器的电阻给出。 电流源电阻中的电阻和负电阻的电阻被控制为基本相同，从而增加电流源电路的输出电阻。 电流源电路用于当从差分输出端子观察时增加输出电阻。 结果，使用该电流源电路实现提供高增益的差分放大器。

公开(公告)号：US07053810B2

公开(公告)日：2006-05-30

申请号：US11151551

申请日：2005-06-14

申请人： Hisashi Harada ,  Takahiro Miki ,  Hideo Matsui

发明人： Hisashi Harada ,  Takahiro Miki ,  Hideo Matsui

IPC分类号： H03M1/34

CPC分类号： H03M1/1225 ,  H03M1/46

摘要： A successive approximation A/D converter includes first and second S/H and comparators sampling and holding first and second external analog input voltages simultaneously and comparing the held, first and second external analog input voltages with a reference voltage to output first and second signals having levels corresponding to resultant comparisons, and a reference voltage generator operative in response to the first and second signals to generate the reference voltage. The two S/H and comparators share the single reference voltage generator. A reduced chip area can be achieved.

摘要翻译： 逐次逼近A / D转换器包括第一和第二S / H，并且比较器同时采样并保持第一和第二外部模拟输入电压，并将保持的，第一和第二外部模拟输入电压与参考电压进行比较，以输出具有 对应于所得到的比较的电平，以及响应于第一和第二信号而工作以产生参考电压的参考电压发生器。 两个S / H和比较器共享单个参考电压发生器。 可以实现减少的芯片面积。

公开(公告)号：US20060044169A1

公开(公告)日：2006-03-02

申请号：US11214723

申请日：2005-08-31

申请人： Osamu Matsumoto ,  Takahiro Miki ,  Yasuo Morimoto

发明人： Osamu Matsumoto ,  Takahiro Miki ,  Yasuo Morimoto

IPC分类号： H03M1/66

CPC分类号： H03M1/0604 ,  H03M1/742

摘要： A current driven D/A converter sets an OFF control voltage (BIAS3) for turning off NMOS transistors M12P, M12N, M22P, M22N, M32P and M32N at a voltage close to an ON control voltage (BIAS2). This makes it possible to reduce the swing of the control voltage (ON control voltage—OFF control voltage) of the NMOS transistors, and hence to reduce the noise due to charge injections through parasitic capacitances, and noise of a ground voltage or power supply voltage due to flowing of discharge currents from the parasitic capacitances to the ground or power supply at turn off of the transistors, thereby being able to offer a high performance current driven D/A converter.

摘要翻译： 电流驱动D / A转换器设置用于在接近ON控制电压（BIAS2）的电压下关断NMOS晶体管M12P，M12N，M22P，M22N，M32P和M32N的OFF控制电压（BIAS3）。 这使得可以减小NMOS晶体管的控制电压（ON控制电压 - 关闭控制电压）的摆动，从而减少由于通过寄生电容的电荷注入引起的噪声，以及接地电压或电源电压的噪声 由于在晶体管截止时由寄生电容放电到地或电源的放电电流的流动，从而能够提供高性能的电流驱动D / A转换器。

公开(公告)号：US06522007B2

公开(公告)日：2003-02-18

申请号：US09974856

申请日：2001-10-12

申请人： Hiroyuki Kouno ,  Toshio Kumamoto ,  Takahiro Miki ,  Hisayasu Satoh

发明人： Hiroyuki Kouno ,  Toshio Kumamoto ,  Takahiro Miki ,  Hisayasu Satoh

IPC分类号： H01L2348

CPC分类号： H01L27/08 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76838 ,  H01L21/823437 ,  H01L23/5227 ,  H01L23/528 ,  H01L29/42372 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A gate electrode has a relatively long gate length of e.g., about 10 &mgr;m. In a region immediately above the gate electrode which is sandwiched between first-layer metals provided is a metal dummy pattern having a width in the first direction and extending in the second direction perpendicular to a direction of gate length (direction of current flow). Moreover, a geometric center of the metal dummy pattern in the second direction is equal to a geometric center of the gate electrode in the second direction. This maintains the symmetry in shape of the metal dummy pattern as viewed from the gate electrode. Such a structure can make deterioration in characteristics of a plurality of elements uniform while maintaining the essential effect of a metal CMP.

摘要翻译： 栅电极具有例如约10μm的较长栅极长度。 在夹在所提供的第一层金属之间的栅电极正上方的区域是具有第一方向的宽度并且沿与栅极长度方向（电流方向）垂直的第二方向延伸的金属虚设图案。 此外，第二方向上的金属虚设图案的几何中心等于栅电极在第二方向上的几何中心。 这保持了从栅电极观察时的金属虚设图形的对称性。 这样的结构可以使多个元件的特性劣化，同时保持金属CMP的基本效果。

公开(公告)号：US06472930B1

公开(公告)日：2002-10-29

申请号：US09177503

申请日：1998-10-23

申请人： Yasuo Morimoto ,  Hiroyuki Kono ,  Takahiro Miki

发明人： Yasuo Morimoto ,  Hiroyuki Kono ,  Takahiro Miki

IPC分类号： G05F110

CPC分类号： G05F3/24

摘要： A current generator (CG) is composed of a constant-current-source transistor M1, and transistors (M2, M3). On receipt of control signals (VG2, VG3) respectively from a driver circuit (not shown), the transistors (M2, M3) complementarily operate to function as current switches. Then, damping resistance (R3) is provided between the drain electrode of the transistor (M3) and an output terminal ({overscore (IT)}). The output terminal ({overscore (IT)}) is connected to a ground (GND), while an output terminal (IT) is grounded via an external terminal (R2). Such a structure allows a semiconductor integrated circuit device to reduce its output ringing and further to suppress imperfections resulting from the adoption of the structure to reduce the ringing.

摘要翻译： 电流发生器（CG）由恒流源晶体管M1和晶体管（M2，M3）组成。 分别从驱动电路（未示出）接收到控制信号（VG2，VG3）时，晶体管（M2，M3）互补地工作，起到电流开关的作用。 然后，在晶体管（M3）的漏电极和输出端（{overscore（IT）}之间设置阻尼电阻（R3）。 输出端子（{overscore（IT）}）连接到地（GND），而输出端（IT）通过外部端子（R2）接地。 这种结构允许半导体集成电路器件减少其输出振铃并且进一步抑制由采用该结构导致的减少振铃的缺陷。

公开(公告)号：US06388502B2

公开(公告)日：2002-05-14

申请号：US09756215

申请日：2001-01-09

申请人： Kazuo Kaneki ,  Takahiro Miki

发明人： Kazuo Kaneki ,  Takahiro Miki

IPC分类号： G06F744

CPC分类号： H03F3/45089 ,  H03D7/1433 ,  H03D7/1458 ,  H03D2200/0088 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2203/45631 ,  H03F2203/45702 ,  H03F2203/45722

摘要： An output signal gain is improved by a semiconductor integrated circuit comprising a mixer circuit having an upper-stage transistor circuit to which a local signal is inputted and a lower-stage transistor circuit to which an RF signal is inputted, wherein a first resistance and a second resistance serving as a load are connected between the upper-stage transistor circuit and supply voltage, and a result of multiplication operation performed via the upper-stage transistor circuit and the lower-stage transistor circuit is made to appear as a first signal and a second signal at the first resistance and the second resistance respectively on the basis of the supply voltage; an emitter follower circuit including a first transistor and a second transistor for respectively receiving outputs from the first resistance and the second resistance and outputting a first amplified signal and a second amplified signal that have been subjected to impedance conversion on the basis of the supply voltage; and an operational amplifier circuit for receiving the first amplified signal on an inverting input side via an input resistance and the second amplified signal on a non-inverting input side, the operational amplifier circuit including a feedback resistance for connecting its output side and the inverting input side provided with the input resistance.

摘要翻译： 输出信号增益由包括具有输入本地信号的上级晶体管电路的混频器电路和输入RF信号的下级晶体管电路的半导体集成电路改进，其中第一电阻和 作为负载的第二电阻连接在上级晶体管电路和电源电压之间，并且经由上级晶体管电路和下级晶体管电路执行的乘法运算的结果作为第一信号和 第二电阻和第二电阻分别基于电源电压; 射极跟随器电路，包括第一晶体管和第二晶体管，用于分别从第一电阻和第二电阻接收输出，并输出基于电源电压进行阻抗转换的第一放大信号和第二放大信号; 以及运算放大器电路，用于经由输入电阻在反相输入侧接收第一放大信号，并且在非反相输入侧接收第二放大信号，运算放大器电路包括用于连接其输出侧和反相输入端的反馈电阻 一侧设有输入电阻。