公开(公告)号：US07924184B1

公开(公告)日：2011-04-12

申请号：US11904008

申请日：2007-09-24

申请人： Allen Chan ,  Sergey Shumarayev ,  Wilson Wong

发明人： Allen Chan ,  Sergey Shumarayev ,  Wilson Wong

IPC分类号： H03M9/00

CPC分类号： H03K19/1732

摘要： An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and a channel of high-speed serial data signal interface (e.g., transceiver) circuitry. To facilitate enabling the integrated circuit to support any of many possible different high-speed serial communication protocols, the channel is hard-wired to include a parallel data bus of fixed width for exchanging parallel data with the programmable circuitry. Regardless of the protocol being implemented, the full width of this bus is always used. A portion of the programmable circuitry is programmed to convert data between the block width and a group width, which can be different from the block width and which is used for the data elsewhere in the integrated circuit.

摘要翻译： 集成电路（例如可编程集成电路，例如可编程微控制器，可编程逻辑器件等）包括可编程电路和高速串行数据信号接口（例如，收发器）电路的通道。 为了使集成电路能够支持许多可能的不同高速串行通信协议中的任何一种，该信道被硬接线以包括用于与可编程电路交换并行数据的固定宽度的并行数据总线。 无论正在执行协议，始终使用该总线的全宽。 可编程电路的一部分被编程为在块宽度和组宽度之间转换数据，其可以与块宽度不同，并且用于集成电路中其他地方的数据。

公开(公告)号：US07920621B2

公开(公告)日：2011-04-05

申请号：US11522284

申请日：2006-09-14

申请人： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

发明人： Wilson Wong ,  Doris Po Ching Chan ,  Sergey Shumarayev ,  Simardeep Maangat ,  Tim Tri Hoang ,  Tin H. Lai ,  Thungoc M. Tran

IPC分类号： H03H7/30

CPC分类号： H04L25/03885

摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.

摘要翻译： 输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。 将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。 该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

公开(公告)号：US07821343B1

公开(公告)日：2010-10-26

申请号：US12229813

申请日：2008-08-27

申请人： Wilson Wong ,  Sergey Shumarayev ,  Allen Chan ,  Weiqi Ding

发明人： Wilson Wong ,  Sergey Shumarayev ,  Allen Chan ,  Weiqi Ding

IPC分类号： H03L7/00

CPC分类号： H03L7/23

摘要： A transmitter that includes a first phase locked loop (PLL) and a second PLL coupled to the first PLL is described. In one implementation, the first PLL is an inductance-capacitance (LC) type PLL and the second PLL is a ring type PLL. Also, in one embodiment, the transmitter further includes a PLL selection multiplexer coupled to the first and second PLLs, where the PLL selection multiplexer receives an output of the first PLL and an output of the second PLL and outputs either the output of the first PLL or the output of the second PLL. In one implementation, a control signal for controlling selection by the PLL selection multiplexer is programmable at runtime. In one implementation, the transmitter of the present invention further includes a clock generation block coupled to the PLL selection multiplexer, a serializer block coupled to the clock generation block and a transmit driver block coupled to the serializer block. In one embodiment, the transmit driver block includes only one post-tap pre-driver and only one main-tap pre-driver. The transmitter of the present invention is capable of operating in a wide range mode or a low jitter mode by selecting the appropriate PLL. In wide range mode, a wider frequency range is desirable. On the other hand, in low jitter mode, a low jitter is desirable.

摘要翻译： 描述了包括耦合到第一PLL的第一锁相环（PLL）和第二PLL的发射机。 在一个实现中，第一PLL是电感 - 电容（LC）型PLL，第二PLL是环型PLL。 此外，在一个实施例中，发射机还包括耦合到第一和第二PLL的PLL选择多路复用器，其中PLL选择多路复用器接收第一PLL的输出和第二PLL的输出，并输出第一PLL的输出 或第二PLL的输出。 在一个实现中，用于控制PLL选择多路复用器的选择的控制信号在运行时可编程。 在一个实现中，本发明的发射机还包括耦合到PLL选择多路复用器的时钟产生模块，耦合到时钟产生模块的串行器模块和耦合到串行器模块的发送驱动器模块。 在一个实施例中，发射驱动器块仅包括一个抽头前驱动器和仅一个主抽头预驱动器。 本发明的发射机能够通过选择适当的PLL在宽范围模式或低抖动模式下工作。 在宽范围模式下，需要较宽的频率范围。 另一方面，在低抖动模式中，需要低抖动。

公开(公告)号：US07773668B1

公开(公告)日：2010-08-10

申请号：US10762864

申请日：2004-01-21

申请人： Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat ,  Rakesh Patel

发明人： Wilson Wong ,  Sergey Shumarayev ,  Simardeep Maangat ,  Rakesh Patel

IPC分类号： H03H7/30 ,  H03H7/40

CPC分类号： H04L25/03044 ,  H04L2025/03356 ,  H04L2025/03579 ,  H04L2025/03783

摘要： A programmable logic device is provided with adaptive equalization circuitry that is programmable in one or more respects. Examples of the programmable aspects of the equalization circuitry are (1) the number of taps used, (2) whether integer or fractional spaced taps are used, (3) what starting values are used in the computation of coefficient values, (4) whether satisfactory coefficient values are computed only once or on an on-going basis, (5) whether an error signal is generated using a decision directed algorithm or using a training pattern, (6) what training pattern (if any) is used, and/or (7) the location of the sampling point in the bit period of the signal to be equalized.

摘要翻译： 可编程逻辑器件设置有可在一个或多个方面可编程的自适应均衡电路。 均衡电路的可编程方面的示例是（1）使用的抽头数量，（2）是否使用整数或分数间隔抽头，（3）在系数值的计算中使用什么起始值，（4）是否 （5）是否使用决策导向算法或使用训练模式生成错误信号，（6）使用何种训练模式（如果有的话）和/ 或者（7）要被均衡的信号的位周期内的采样点的位置。

公开(公告)号：US07760799B2

公开(公告)日：2010-07-20

申请号：US11238365

申请日：2005-09-28

申请人： Tin H. Lai ,  Sergey Shumarayev ,  Simardeep Maangat ,  Wilson Wong

发明人： Tin H. Lai ,  Sergey Shumarayev ,  Simardeep Maangat ,  Wilson Wong

IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC分类号： H03G3/3089 ,  H04L25/03885

摘要： Equalization circuitry may be used to compensate for the attenuation of a data signal caused by a transmission medium. The control circuitry for the equalization circuitry may generate control inputs for equalization stages that control the amount of gain provided to the data signal. A comparator may determine whether the gain from the equalization circuitry is less than or more than the desired amount of gain. A programmable up/down counter may adjust the counter value based on the output of the comparator. The counter value may be converted into one or more analog voltages using one or more digital-to-analog converters. These analog voltages may be provided to the equalization stages as control inputs. The control circuitry may also include hysteresis circuitry that prevents the counter value from being adjusted when the gain produced by the equalization stages is close to the desired amount of gain.

摘要翻译： 均衡电路可用于补偿由传输介质引起的数据信号的衰减。 用于均衡电路的控制电路可以产生用于控制提供给数据信号的增益量的均衡级的控制输入。 比较器可以确定来自均衡电路的增益是否小于或大于期望的增益量。 可编程上/下计数器可以根据比较器的输出来调整计数器值。 可以使用一个或多个数模转换器将计数器值转换成一个或多个模拟电压。 这些模拟电压可以作为控制输入提供给均衡级。 控制电路还可以包括滞后电路，当由均衡级产生的增益接近期望的增益量时，阻止计数器值被调整。

公开(公告)号：US20100090774A1

公开(公告)日：2010-04-15

申请号：US12277810

申请日：2008-11-25

申请人： Sergey Shumarayev ,  Wilson Wong ,  Allen Chan ,  Ali Atesoglu

发明人： Sergey Shumarayev ,  Wilson Wong ,  Allen Chan ,  Ali Atesoglu

IPC分类号： H03B5/18

CPC分类号： H03B5/1228 ,  H03B5/1215 ,  H03B5/1243 ,  H03B5/1265 ,  H03B2201/011

摘要： An oscillator circuit includes transistors that are cross-coupled through routing conductors in a first conductive layer. The oscillator circuit also includes a varactor, a capacitor, and an option conductor in a second conductive layer. The option conductor forms at least a portion of a connection between one of the transistors and the capacitor or the varactor.

摘要翻译： 振荡器电路包括通过第一导电层中的路由导体交叉耦合的晶体管。 振荡器电路还包括第二导电层中的变容二极管，电容器和选项导体。 选项导体形成晶体管之一和电容器或变容二极管之间的连接的至少一部分。

公开(公告)号：US07688106B1

公开(公告)日：2010-03-30

申请号：US11712609

申请日：2007-02-27

申请人： Sergey Shumarayev ,  Thungoc M. Tran ,  Simardeep Maangat ,  Wilson Wong

发明人： Sergey Shumarayev ,  Thungoc M. Tran ,  Simardeep Maangat ,  Wilson Wong

IPC分类号： H03K19/173

CPC分类号： H03K19/17744

摘要： High-speed serial interface (“HSSI”) transceiver circuitry (e.g., on a programmable logic device (“PLD”) integrated circuit) includes input buffer circuitry with adaptive equalization capability. The transceiver circuitry also includes an output driver, which may include pre-emphasis capability (preferably controllably settable). Selectively usable loop-back circuitry is provided for allowing the output signal of the input buffer to be applied substantially directly to the output driver. The loop-back circuitry may include a loop-back driver, which may be turned on substantially only when needed for loop-back operations.

摘要翻译： 高速串行接口（“HSSI”）收发器电路（例如，在可编程逻辑器件（“PLD”）集成电路上）包括具有自适应均衡能力的输入缓冲器电路。 收发器电路还包括输出驱动器，其可以包括预加重功能（优选可控地设置）。 提供了可选择的环回电路，用于使输入缓冲器的输出信号基本上直接施加到输出驱动器。 环回电路可以包括环回驱动器，其可以基本上仅在环回操作需要时被导通。

公开(公告)号：US07659745B1

公开(公告)日：2010-02-09

申请号：US12218688

申请日：2008-07-16

申请人： Wilson Wong ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang

发明人： Wilson Wong ,  Sergey Shumarayev ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC分类号： H03K19/0175 ,  H03K5/00 ,  G06F7/38

CPC分类号： H03K19/17744

摘要： A programmable logic device (“PLD”) includes circuitry for optionally and variably modifying characteristics of an input signal in any of several respects. Examples of such modifications include AC coupling the signal into the PLD, low pass filtering the signal (with selectable low-pass filter corner frequency), shifting the common voltage of the input signal, and/or subjecting the input signal to a selectable amount of attenuation.

摘要翻译： 可编程逻辑器件（“PLD”）包括用于在几个方面中的任何一个中可选地且可变地修改输入信号的特性的电路。 这样的修改的示例包括将信号AC耦合到PLD中，对信号进行低通滤波（具有可选择的低通滤波器转角频率），移位输入信号的公共电压，和/或使输入信号经受可选择量的 衰减。

公开(公告)号：US20090285275A1

公开(公告)日：2009-11-19

申请号：US12511022

申请日：2009-07-28

申请人： Wilson Wong ,  Rakesh H. Patel ,  Sergey Shumarayev ,  Tin H. Lai

发明人： Wilson Wong ,  Rakesh H. Patel ,  Sergey Shumarayev ,  Tin H. Lai

IPC分类号： H04L27/01

CPC分类号： H04B7/005 ,  H04L25/03006 ,  H04L25/061

摘要： Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies but not for low frequencies. For low frequency adjustment, the control block controls the normalized signal amplitude in the signal normalization block. In this manner, controlled adjustment for low frequency content is performed in the signal normalization block.

摘要翻译： 公开了一种用于调整从通信路径接收的信号的系统和方法。 接收机可以接收来自衰减信号的至少一些频率分量的通信路径的信号。 接收机可以包括调整接收信号的频率内容中的至少一些的均衡块，提供归一化信号幅度和/或归一化边沿斜率的信号归一化块以及控制块。 在一个实施例中，控制块控制用于高频而不是低频的均衡块中的频率调整。 对于低频调整，控制块控制信号归一化块中的归一化信号幅度。 以这种方式，在信号归一化块中执行低频内容的受控调整。

公开(公告)号：US07590207B1

公开(公告)日：2009-09-15

申请号：US11256346

申请日：2005-10-20

申请人： Sergey Y Shumarayev ,  Rakesh H Patel ,  Wilson Wong ,  Tim Tri Hoang ,  William Bereza

发明人： Sergey Y Shumarayev ,  Rakesh H Patel ,  Wilson Wong ,  Tim Tri Hoang ,  William Bereza

IPC分类号： H04L7/00

CPC分类号： H03L7/087 ,  H04J3/0688 ,  H04L7/033

摘要： A serial interface for a programmable logic device can be used as a conventional high-speed quad interface, but also allows an individual channel, if not otherwise being used, to be programmably configured as a loop circuit (e.g., a phase-locked loop). This is accomplished by disabling the data loop of clock-data recovery circuitry in the channel, and reconfiguring the reference loop to operate as a loop circuit. In addition, instead of providing a high-speed quad interface having four channels and one or more clock management units (CMUs), a more flexible interface having five or more channels can be provided, and when it is desired to use the interface as a high-speed quad interface, one or more channels can be configured as loop circuits to function as CMUs.

摘要翻译： 用于可编程逻辑器件的串行接口可以用作传统的高速四边形接口，但是也允许单独的通道（如果不另外使用）被可编程地配置为环路电路（例如，锁相环） 。 这是通过禁用通道中的时钟数据恢复电路的数据循环来实现的，并且重新配置参考环路以用作循环电路。 此外，不是提供具有四个通道的高速四边形接口和一个或多个时钟管理单元（CMU），而是可以提供具有五个或更多个通道的更灵活的接口，并且当希望将接口用作 高速四通道接口，一个或多个通道可以配置为循环电路，用作CMU。