公开(公告)号：US06793779B2

公开(公告)日：2004-09-21

申请号：US10369856

申请日：2003-02-20

Applicant: Peijun Ding ,  Tony Chiang ,  Barry L. Chin

Inventor： Peijun Ding ,  Tony Chiang ,  Barry L. Chin

IPC: C23C1434

CPC classification number: H01L21/76877 ,  H01L21/2855

Abstract: A method of filling trenches or vias on a semiconductor workpiece surface with copper using sputtering techniques. A copper wetting layer and a copper fill layer may both be applied by sputtering techniques. The thin wetting layer of copper is applied at a substrate surface temperature ranging between about 20° C. to about 250° C., and subsequently the temperature of the substrate is increased, with the application of the sputtered copper fill layer beginning at above at least about 200° C. and continuing while the substrate temperature is increased to a temperature as high as about 600° C. Preferably the substrate temperature during application of the sputtered fill layer ranges between about 300° C. and about 500° C.

Abstract translation: 使用溅射技术用铜填充半导体工件表面上的沟槽或通孔的方法。 铜浸润层和铜填充层都可以通过溅射技术施加。 在约20℃至约250℃范围内的衬底表面温度下施加铜的薄润湿层，随后随着溅射铜填充层的应用从上方开始施加，衬底的温度升高 至少约200℃，并且在衬底温度升高至高达约600℃的温度下继续进行。优选地，溅射填充层施加期间的衬底温度范围为约300℃至约500℃。

公开(公告)号：US06287977B1

公开(公告)日：2001-09-11

申请号：US09126890

申请日：1998-07-31

Applicant: Imran Hashim ,  Tony Chiang ,  Barry Chin

Inventor： Imran Hashim ,  Tony Chiang ,  Barry Chin

IPC: H01L21302

CPC classification number: H01L21/76844 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and forming via-to-via leakage current paths therein. In a second aspect, a capping dielectric barrier layer is deposited over the first metal layer prior to sputter etching. During sputter-etching, the capping dielectric barrier layer redistributes on the sidewalls of the interlayer dielectric, preventing sputter-etched copper atoms from reaching the interlayer dielectric and forming via-to-via leakage paths therein. In a third aspect, both a capping dielectric barrier layer and a barrier layer are deposited over the first metal layer prior to sputter-etching to prevent copper atoms produced during sputter-etching from reaching the interlayer dielectric and forming via-to-via leakage paths therein.

Abstract translation: 公开了形成没有通孔到通孔泄漏电流并具有低电阻的铜互连的方法。 在第一方面，在铜氧化物溅射蚀刻之前，在第一金属层上沉积阻挡层，以防止铜原子到达层间电介质，并在其中形成通孔到漏电流路径。 在第二方面，在溅射蚀刻之前，在第一金属层上沉积封盖电介质阻挡层。 在溅射蚀刻期间，封盖电介质阻挡层重新分布在层间电介质的侧壁上，防止溅射蚀刻的铜原子到达层间电介质并在其中形成通孔到通孔泄漏路径。 在第三方面，在溅射蚀刻之前，在第一金属层上沉积封盖介电阻挡层和阻挡层，以防止在溅射蚀刻期间产生的铜原子到达层间电介质并形成通孔到通孔泄漏路径 其中。

公开(公告)号：US08975613B1

公开(公告)日：2015-03-10

申请号：US12610236

申请日：2009-10-30

Applicant: Ronald John Kuse ,  Tony Chiang ,  Michael Miller ,  Prashant Phatak ,  Jinhong Tong

Inventor： Ronald John Kuse ,  Tony Chiang ,  Michael Miller ,  Prashant Phatak ,  Jinhong Tong

IPC: H01L21/16 ,  G11C11/00

CPC classification number: H01L45/146 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/32 ,  G11C2213/51 ,  G11C2213/52 ,  G11C2213/56 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/74 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/861 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1616 ,  H01L45/1641

Abstract: Resistive-switching memory elements having improved switching characteristics are described, including a memory element having a first electrode and a second electrode, a switching layer between the first electrode and the second electrode, the switching layer comprising a first metal oxide having a first bandgap greater than 4 electron volts (eV), the switching layer having a first thickness, and a coupling layer between the switching layer and the second electrode, the coupling layer comprising a second metal oxide having a second bandgap greater the first bandgap, the coupling layer having a second thickness that is less than 25 percent of the first thickness.

公开(公告)号：US08659001B2

公开(公告)日：2014-02-25

申请号：US13223950

申请日：2011-09-01

Applicant: Yun Wang ,  Tony Chiang ,  Imran Hashim

Inventor： Yun Wang ,  Tony Chiang ,  Imran Hashim

IPC: H01L47/00

CPC classification number: H01L45/122 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/146 ,  H01L45/1608

Abstract: Embodiments of the present invention generally relate to a resistive switching nonvolatile memory element that is formed in a resistive switching memory device that may be used in a memory array to store digital data. The memory element is generally constructed as a metal-insulator-metal stack. The resistive switching portion of the memory element includes a getter portion and/or a defect portion. In general, the getter portion is an area of the memory element that is used to help form, during the resistive switching memory device's fabrication process, a region of the resistive switching layer that has a greater number of vacancies or defects as compared to the remainder of resistive switching layer. The defect portion is an area of the memory element that has a greater number of vacancies or defects as compared to the remainder of the resistive switching layer, and is formed during the resistive switching memory device's fabrication process. The addition of the getter or defect portions in a formed memory device generally improves the reliability of the resistive switching memory device, improves the switching characteristics of the formed memory device and can eliminate or reduce the need for the time consuming additional post fabrication “burn-in” or pre-programming steps.

Abstract translation: 本发明的实施例一般涉及一种电阻式开关非易失性存储元件，其形成在电阻式开关存储器件中，其可用于存储阵列中以存储数字数据。 存储元件通常构造为金属 - 绝缘体 - 金属叠层。 存储元件的电阻开关部分包括吸气部分和/或缺陷部分。 通常，吸气剂部分是存储元件的区域，其用于帮助在电阻式开关存储器件的制造过程期间形成与其余部分相比具有更多数量的空位或缺陷的电阻式开关层的区域 的电阻式开关层。 缺陷部分是与电阻开关层的其余部分相比具有更多数量的空位或缺陷的存储元件的区域，并且在电阻式开关存储器件的制造过程期间形成。 吸收剂或缺陷部分在形成的存储器件中的添加通常提高了电阻式开关存储器件的可靠性，改进了所形成的存储器件的开关特性，并且可以消除或减少耗费时间的附加后制造“ 在“或预编程步骤。

公开(公告)号：US08618525B2

公开(公告)日：2013-12-31

申请号：US13156624

申请日：2011-06-09

Applicant: Yun Wang ,  Tony Chiang ,  Imran Hashim

Inventor： Yun Wang ,  Tony Chiang ,  Imran Hashim

IPC: H01L47/00

CPC classification number: H01L45/1608 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/065 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1616 ,  H01L45/1633 ,  H01L45/1641

Abstract: Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.

公开(公告)号：US08546275B2

公开(公告)日：2013-10-01

申请号：US13236481

申请日：2011-09-19

Applicant: Yun Wang ,  Vidyut Gopal ,  Imran Hashim ,  Dipankar Pramanik ,  Tony Chiang

Inventor： Yun Wang ,  Vidyut Gopal ,  Imran Hashim ,  Dipankar Pramanik ,  Tony Chiang

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L45/146 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1616

Abstract: Embodiments of the invention generally relate to nonvolatile memory devices and methods for manufacturing such memory devices. The methods for forming improved memory devices, such as a ReRAM cells, provide optimized, atomic layer deposition (ALD) processes for forming a metal oxide film stack having a metal oxide buffer layer disposed on or over a metal oxide bulk layer. The metal oxide bulk layer contains a metal-rich oxide material and the metal oxide buffer layer contains a metal-poor oxide material. The metal oxide bulk layer is less electrically resistive than the metal oxide buffer layer since the metal oxide bulk layer is less oxidized or more metallic than the metal oxide buffer layer. In one example, the metal oxide bulk layer contains a metal-rich hafnium oxide material and the metal oxide buffer layer contains a metal-poor zirconium oxide material.

Abstract translation: 本发明的实施例一般涉及用于制造这种存储器件的非易失性存储器件和方法。 用于形成改进的存储器件（例如ReRAM单元）的方法提供优化的原子层沉积（ALD）工艺，用于形成金属氧化物膜堆叠，其具有设置在金属氧化物本体层上或其上的金属氧化物缓冲层。 金属氧化物本体层含有富金属氧化物材料，金属氧化物缓冲层含有贫金属氧化物。 由于金属氧化物本体层比金属氧化物缓冲层氧化较少或更金属，所以金属氧化物本体层的电阻小于金属氧化物缓冲层的电阻。 在一个实例中，金属氧化物本体层含有富金属氧化铪材料，金属氧化物缓冲层含有贫金属氧化锆材料。

公开(公告)号：US08535972B2

公开(公告)日：2013-09-17

申请号：US12172110

申请日：2008-07-11

Applicant: Zachary M. Fresco ,  Chi-I Lang ,  Jinhong Tong ,  Anh Duong ,  Nitin Kumar ,  Anna Tsimelzon ,  Tony Chiang

Inventor： Zachary M. Fresco ,  Chi-I Lang ,  Jinhong Tong ,  Anh Duong ,  Nitin Kumar ,  Anna Tsimelzon ,  Tony Chiang

IPC: H01L51/40

CPC classification number: H01L23/5329 ,  C09D129/04 ,  H01L21/02063 ,  H01L21/02074 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of modifying a patterned semiconductor substrate are presented including: providing a patterned semiconductor substrate surface including a dielectric region and a conductive region; and applying an amphiphilic surface modifier to the dielectric region to modify the dielectric region. In some embodiments, modifying the dielectric region includes modifying a wetting angle of the dielectric region. In some embodiments, modifying the wetting angle includes making a surface of the dielectric region hydrophilic. In some embodiments, methods further include applying an aqueous solution to the patterned semiconductor substrate surface. In some embodiments, the conductive region is selectively enhanced by the aqueous solution. In some embodiments, methods further include providing the dielectric region formed of a low-k dielectric material. In some embodiments, applying the amphiphilic surface modifier modifies an interaction of the low-k dielectric region with a subsequent process.

公开(公告)号：US08465996B2

公开(公告)日：2013-06-18

申请号：US13593116

申请日：2012-08-23

Applicant: Michael Miller ,  Prashant Phatak ,  Tony Chiang ,  Xiyang Chen ,  April Schricker ,  Tanmay Kumar

Inventor： Michael Miller ,  Prashant Phatak ,  Tony Chiang ,  Xiyang Chen ,  April Schricker ,  Tanmay Kumar

IPC: H01L21/00

CPC classification number: H01L45/16 ,  H01L21/265 ,  H01L21/31155 ,  H01L27/2463 ,  H01L29/8615 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

公开(公告)号：US08440990B2

公开(公告)日：2013-05-14

申请号：US13156722

申请日：2011-06-09

Applicant: Yun Wang ,  Tony Chiang ,  Imran Hashim

Inventor： Yun Wang ,  Tony Chiang ,  Imran Hashim

IPC: H01L29/00

CPC classification number: H01L45/1608 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/065 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625

Abstract: Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.

公开(公告)号：US08367463B2

公开(公告)日：2013-02-05

申请号：US13111230

申请日：2011-05-19

Applicant: Pragati Kumar ,  Sandra G. Malhotra ,  Sean Barstow ,  Tony Chiang

Inventor： Pragati Kumar ,  Sandra G. Malhotra ,  Sean Barstow ,  Tony Chiang

IPC: H01L21/00 ,  H01L21/16 ,  H01L21/20 ,  H01L21/36

CPC classification number: H01L45/1625 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1641

Abstract: Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed from resistive-switching metal oxide layers. Metal oxide layers may be formed using sputter deposition at relatively low sputtering powers, relatively low duty cycles, and relatively high sputtering gas pressures. Dopants may be incorporated into a base oxide layer at an atomic concentration that is less than the solubility limit of the dopant in the base oxide. At least one oxidation state of the metal in the base oxide is preferably different than at least one oxidation sate of the dopant. The ionic radius of the dopant and the ionic radius of the metal may be selected to be close to each other. Annealing and oxidation operations may be performed on the resistive switching metal oxides. Bistable metal oxides with relatively large resistivities and large high-state-to-low state resistivity ratios may be produced.

Abstract translation: 提供具有电阻开关金属氧化物的非易失性存储元件。 非易失性存储元件可以由电阻式开关金属氧化物层形成。 金属氧化物层可以使用相对低的溅射功率，相对低的占空比和较高的溅射气体压力的溅射沉积形成。 掺杂剂可以以小于基底氧化物中的掺杂剂的溶解度极限的原子浓度结合到基底氧化物层中。 基底氧化物中金属的至少一种氧化态优选不同于掺杂剂的至少一种氧化态。 可以选择掺杂剂的离子半径和金属的离子半径彼此接近。 可以对电阻式开关金属氧化物进行退火和氧化操作。 可以制造具有相对较大的电阻率和大的高 - 低 - 电阻率比的双稳态金属氧化物。