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195 条记录 (耗时 0.042 秒)

    Semiconductor wafer and manufacturing method thereof
    74.
    发明授权
    Semiconductor wafer and manufacturing method thereof 失效
    半导体晶片及其制造方法

    公开(公告)号：US07291542B2

    公开(公告)日：2007-11-06

    申请号：US11223970

    申请日：2005-09-13

    申请人： Toshiaki Iwamatsu ,  Shigenobu Maeda

    发明人： Toshiaki Iwamatsu ,  Shigenobu Maeda

    IPC分类号： H01L21/30 ,  H01L21/46

    CPC分类号： H01L21/76243 ,  H01L21/02027 ,  H01L21/67092 ,  H01L21/68 ,  H01L21/76254 ,  H01L21/76256 ,  H01L23/544 ,  H01L29/045 ,  H01L29/78606 ,  H01L29/78654 ,  H01L29/78696 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor wafer and its manufacturing method are provided where the current driving capability of a MOS transistor can be sufficiently enhanced. An SOI layer wafer in which an SOI layer (32) is formed has a crystal direction notch (32a) and a crystal direction notch (32b). The SOI layer wafer and a supporting substrate wafer (1) are bonded to each other in such a way that the notch (32a) and a crystal direction notch (1a) of the supporting substrate wafer (1) coincide with each other. When bonding the two wafers by using the notch (32a) and the notch (1a) to position the two wafers, the other notch (32b) of the SOI layer wafer can be engaged with a guide member of the semiconductor wafer manufacturing apparatus to prevent positioning error due to relative turn between the wafers. Thus an MOS transistor with a sufficiently improved current driving capability can be fabricated on the semiconductor wafer with the two wafers positioned in crystal directions shifted from each other.

    摘要翻译： 提供一种可以充分提高MOS晶体管的电流驱动能力的半导体晶片及其制造方法。 其中形成SOI层（32）的SOI层晶片具有<100>晶向切口（32a）和<110>晶体方向凹口（32b）。 SOI层晶片和支撑基板晶片（1）彼此接合，使得支撑基板晶片（1）的凹口（23a）和（110）晶体方向缺口（1a）与 彼此。 当通过使用凹口（32a）和凹口（1a）将两个晶片接合以定位两个晶片时，SOI层晶片的另一个凹口（32b）可以与半导体晶片制造的引导构件接合 用于防止由于晶片之间的相对转动引起的定位误差的装置。 因此，可以在半导体晶片上制造具有充分改善的电流驱动能力的MOS晶体管，其中两个晶片位于晶体方向彼此偏移。

    Semiconductor device having a trench isolation and method of fabricating the same
    76.
    发明申请
    Semiconductor device having a trench isolation and method of fabricating the same 失效
    具有沟槽隔离的半导体器件及其制造方法

    公开(公告)号：US20070032001A1

    公开(公告)日：2007-02-08

    申请号：US11543213

    申请日：2006-10-05

    申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto ,  Shigenobu Maeda

    发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Takuji Matsumoto ,  Shigenobu Maeda

    IPC分类号： H01L21/84 ,  H01L21/336

    CPC分类号： H01L21/2652 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203

    摘要： The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.

    摘要翻译： 本发明提供一种制造半导体器件的方法，其中通过防止在有源区中形成沟道阻挡注入层来防止晶体管特性的劣化。 形成抗蚀剂掩模，以便在形成PMOS晶体管的区域上具有开口。 通过离子通过部分隔离氧化膜的能量进行沟道停止注入，在SOI层中产生杂质分布的峰，从而在部分隔离氧化膜的SOI层内形成沟道停止层，即 ，隔离区域。 这里要植入的杂质是N型杂质。 在使用磷的情况下，其注入能量设定为例如60至120keV，并且通道阻挡层的密度设定为1×10 17至1×10 19 / SUP> / cm 3。 此时，沟道停止注入的杂质在与有源区对应的SOI层中不停止。

    Method of manufacturing semiconductor device having trench isolation
    77.
    发明授权
    Method of manufacturing semiconductor device having trench isolation 失效
    制造具有沟槽隔离的半导体器件的方法

    公开(公告)号：US07144764B2

    公开(公告)日：2006-12-05

    申请号：US10949451

    申请日：2004-09-27

    申请人： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

    发明人： Takuji Matsumoto ,  Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Shigeto Maegawa

    IPC分类号： H01L21/762

    CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1203 ,  H01L29/78609 ,  H01L29/78612

    摘要： The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).

    摘要翻译： 本发明涉及制造半导体器件的方法的改进，其中通过防止在有源区中形成沟道阻挡注入层来避免晶体管特性的劣化。 在图案化氮化膜（22）之后，测量SOI层3的厚度（S 2），并且通过使用测量结果，确定用于SOI层3的蚀刻条件（蚀刻时间等）（S 3） 。 为了测量SOI层3的厚度，使用用线偏振光照射物质表面的光谱椭偏仪，并观察到由物质表面反射的椭圆偏振光就足够了。 使用所确定的蚀刻条件，并且通过使用图案化的氮化物膜22作为蚀刻掩模形成沟槽TR 2（S 4）。

    Semiconductor device
    78.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20060237726A1

    公开(公告)日：2006-10-26

    申请号：US11409040

    申请日：2006-04-24

    申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Tatsuhiko Ikeda ,  Shigeto Maegawa

    发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi ,  Tatsuhiko Ikeda ,  Shigeto Maegawa

    IPC分类号： H01L29/04

    CPC分类号： H01L27/0811 ,  H01L27/1203

    摘要： While improving the frequency characteristics of a decoupling capacitor, suppressing the voltage drop of a source line and stabilizing it, the semiconductor device which suppressed decline in the area efficiency of decoupling capacitor arrangement is offered. Decoupling capacitors DM1 and DM2 are connected between the source line connected to the pad for high-speed circuits which supplies electric power to circuit block C1, and the ground line connected to a ground pad, and the capacitor array for high-speed circuits is formed. A plurality of decoupling capacitor DM1 are connected between the source line connected to the pad for low-speed circuits which supplies electric power to circuit block C2, and the ground line connected to a ground pad, and the capacitor array for low-speed circuits is formed. Decoupling capacitor DM1 differs in the dimension of a gate electrode from DM2.

    摘要翻译： 在提高去耦电容器的频率特性的同时，抑制源极线路的电压降并使其稳定，从而提供抑制去耦电容器布置的面积效率下降的半导体器件。 去耦电容器DM1和DM2连接在连接到用于为电路块C 1供电的高速电路的焊盘的源极线和连接到接地焊盘的地线之间，并且用于高速的电容器阵列 形成电路。 多个去耦电容器DM1连接在连接到用于向电路块C 2供电的低速电路的焊盘的源极线和连接到接地焊盘的地线之间，以及用于低速的电容器阵列 形成电路。 去耦电容器DM 1的栅电极尺寸与DM2不同。

    Semiconductor device and method of manufacturing the same
    79.
    发明申请
    Semiconductor device and method of manufacturing the same 审中-公开
    半导体装置及其制造方法

    公开(公告)号：US20060186474A1

    公开(公告)日：2006-08-24

    申请号：US11408181

    申请日：2006-04-21

    申请人： Takuji Matsumoto ,  Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

    发明人： Takuji Matsumoto ,  Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

    IPC分类号： H01L27/12

    CPC分类号： H01L29/78615 ,  H01L21/76264 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1112 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78654 ,  Y10S257/904

    摘要： It is an object to provide a semiconductor device having an SOI structure in which an electric potential of a body region in an element formation region isolated by a partial isolation region can be fixed with a high stability. A MOS transistor comprising a source region (51), a drain region (61) and an H gate electrode (71) is formed in an element formation region isolated by a partial oxide film (31). The H gate electrode (71) electrically isolates a body region (13) formed in a gate width W direction adjacently to the source region (51) and the drain region (61) from the drain region (61) and the source region (51) through “I” in a transverse direction (a vertical direction in the drawing), a central “−” functions as a gate electrode of an original MOS transistor.

    摘要翻译： 本发明的目的是提供具有SOI结构的半导体器件，其中可以以高稳定性固定由部分隔离区隔离的元件形成区域中的体区的电位。 在由部分氧化膜（31）隔离的元件形成区域中形成包括源极区（51），漏极区（61）和H栅电极（71）的MOS晶体管。 H栅电极（71）将从栅极宽度W方向形成的主体区域（13）与漏极区域（61）和源极区域（51）的源极区域（51）和漏极区域（61）相邻地隔离 ）通过“I”横向（图中的垂直方向），中心“ - ”用作原始MOS晶体管的栅电极。