公开(公告)号：US5321939A

公开(公告)日：1994-06-21

申请号：US950291

申请日：1992-09-24

申请人： Shinya Fuse ,  Tadashi Shimada ,  Akio Noji ,  Naoki Kinoshita ,  Toshikazu Nakamura ,  Hironori Kato

发明人： Shinya Fuse ,  Tadashi Shimada ,  Akio Noji ,  Naoki Kinoshita ,  Toshikazu Nakamura ,  Hironori Kato

IPC分类号： A01D34/63 ,  A01D43/063 ,  A01D75/28

CPC分类号： A01D43/0631 ,  A01D2101/00 ,  A01D34/63 ,  Y10S56/15

摘要： A transmission type light sensor is disposed in the vicinity of the exit of a shooter, which has the exit thereof positioned above a grass-bag opening, and the fullness of the grass-bag is detected when the light blocking state of the sensor continues longer than a predetermined time. A light emitting portion and a light receiving portion of the light sensor are positioned opposite to each other so that their optical axes are in coincidence, and they are firmly attached to both ends of a light sensor mounting member. The light sensor consists of a light sensor main body which is placed at one side of a cover, and a retroreflective board placed at the side of the cover opposite to the light sensor main body for reflecting incident light from the light emitting portion in the direction of incidence.

摘要翻译： 透射型光传感器设置在射出器的出口附近，其射出位于草袋开口上方，并且当传感器的遮光状态持续更长时检测草袋的丰满度 比预定时间。 光传感器的发光部分和光接收部分彼此相对设置，使得其光轴重合，并且它们牢固地附接到光传感器安装部件的两端。 光传感器由放置在盖的一侧的光传感器主体和位于盖的与光传感器主体相对的一侧的反光板组成，用于将来自发光部的入射光反射 的发病率。

公开(公告)号：US20140106961A1

公开(公告)日：2014-04-17

申请号：US14124292

申请日：2012-06-06

申请人： Toru Nakai ,  Yoshinori Funaki ,  Toshikazu Nakamura

发明人： Toru Nakai ,  Yoshinori Funaki ,  Toshikazu Nakamura

IPC分类号： B01J31/38 ,  B01J23/745

CPC分类号： B01J31/38 ,  B01J21/063 ,  B01J23/745 ,  B01J35/004 ,  B01J35/06 ,  B01J37/0215 ,  B01J37/0219 ,  G02B1/18 ,  G02B27/0006

摘要： Provided is a photocatalytic coating film that can develop excellent photocatalytic activity and exhibit superior adhesion to an adherend surface.The photocatalytic coating film is obtained by applying and drying a photocatalytic coating composition containing at least rod-like or needle-like titanium oxide particles and a binder component so that the photocatalytic coating film contains the titanium oxide particles in a content of 0.5 g/m2 or more. The photocatalytic coating film contains the titanium oxide particle in a content per unit volume (1 m2 by 1 μm thick) of less than 3.0 g. The titanium oxide particles preferably have an aspect ratio of 1.5 or more, the aspect ratio specified as the ratio of a long side length to a short side length of particle. The compositional ratio (by weight) of the titanium oxide particles to the binder component in the photocatalytic coating film is preferably from 1:6 to 30:1.

摘要翻译： 提供了可以显现出优异的光催化活性并且表现出对被粘物表面的优异粘附性的光催化涂膜。 通过涂布和干燥含有至少棒状或针状二氧化钛颗粒和粘合剂成分的光催化涂料组合物，使得光催化涂膜含有0.5g / m 2的氧化钛颗粒，得到光催化涂膜 或者更多。 光催化涂膜含有小于3.0g的每单位体积（1m 2×1μm）的氧化钛粒子。 优选氧化钛粒子的纵横比为1.5以上，纵横比规定为长边长与粒子的短边长的比例。 光催化性涂膜中的氧化钛粒子与粘合剂成分的组成比（重量比）优选为1:6〜30:1。

公开(公告)号：US08233347B2

公开(公告)日：2012-07-31

申请号：US12631353

申请日：2009-12-04

申请人： Toshikazu Nakamura ,  Atsushi Takeuchi ,  Atsushi Nakakubo

发明人： Toshikazu Nakamura ,  Atsushi Takeuchi ,  Atsushi Nakakubo

IPC分类号： G11C5/14 ,  G11C8/00

CPC分类号： G11C8/08 ,  G11C5/145 ,  G11C8/18 ,  G11C11/406 ,  G11C11/4074

摘要： A semiconductor memory includes: a voltage supply circuit which supplies a first voltage to a word line when an internal circuit is in a standby state, and supplies a second voltage higher than the first voltage to the word line when the internal circuit is in an active state; and a control circuit changes a drive capacity of the voltage supply circuit when changing from the standby state to the active state and the second voltage is supplied to the word line.

摘要翻译： 半导体存储器包括：当内部电路处于待机状态时向字线提供第一电压的电压供应电路，并且当内部电路处于活动状态时将高于第一电压的第二电压提供给字线 州; 并且当从待机状态变为激活状态并且第二电压被提供给字线时，控制电路改变电压供应电路的驱动能力。

公开(公告)号：US20100321983A1

公开(公告)日：2010-12-23

申请号：US12718819

申请日：2010-03-05

申请人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

发明人： Masato Takita ,  Masato Matsumiya ,  Satoshi Eto ,  Toshikazu Nakamura ,  Masatomo Hasegawa ,  Ayako Kitamoto ,  Kuninori Kawabata ,  Hideki Kanou ,  Toru Koga ,  Yuki Ishii ,  Shinichi Yamada ,  Kaoru Mori

IPC分类号： G11C11/24 ,  G11C5/14

CPC分类号： G11C5/147 ,  G11C8/08 ,  G11C8/12 ,  G11C11/4074 ,  G11C11/4085 ,  G11C2207/2227

摘要： A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.

摘要翻译： 半导体器件包括字线驱动电路，用于通过驱动连接到存储单元的字线来重置字线，并且被构造成切换在复位时设置的字线驱动电路的复位电平 在诸如地电位的第一电位和诸如负电位的第二电位之间的字线的操作。 此外，包括通过布置多个存储单元形成的存储单元阵列和用于产生负电位的字线复位电平发生电路的半导体器件使得可以改变字线复位电平产生电路的电流供应量 当通过将字线复位电平产生电路的输出施加到未被选择的字线而将未被选择的字线设置为负电位时，根据操作来改变负电位的电流供给量 存储单元阵列。 此外，在具有振荡电路和电容器的多个电源电路的半导体装置中，通过由振荡电路输出的振荡信号来驱动电容器，这些电源电路的至少一部分共享振荡 电路，不同的电容器由共同的振荡电路输出的振荡信号驱动。

公开(公告)号：US07649446B2

公开(公告)日：2010-01-19

申请号：US11698024

申请日：2007-01-26

申请人： Kazumi Miyashita ,  Kazutomo Nishida ,  Toshikazu Nakamura ,  Toru Taniguchi

发明人： Kazumi Miyashita ,  Kazutomo Nishida ,  Toshikazu Nakamura ,  Toru Taniguchi

IPC分类号： B60Q1/00

CPC分类号： F01M11/12

摘要： A multipurpose engine controller comprises a control unit for switching between supplying and stopping power supplied from an ignition circuit to a spark plug on the basis of two states, i.e., the operating state of the multipurpose engine determined based on a detection signal from the engine speed sensor, and the state of the level of the oil inside the crankcase determined based on a detection signal from the float-type oil level sensor.

摘要翻译： 多用途发动机控制器包括控制单元，用于基于两种状态，即基于来自发动机转速的检测信号确定的多用途发动机的运行状态，在从点火电路供应到火花塞的供电和停止供电之间进行切换 传感器以及基于来自浮子式油位传感器的检测信号确定的曲轴箱内的油位的状态。

公开(公告)号：US20090077432A1

公开(公告)日：2009-03-19

申请号：US12273270

申请日：2008-11-18

申请人： Toshikazu Nakamura ,  Akira Kikutake ,  Kuninori Kawabata ,  Yasuhiro Onishi ,  Satoshi Eto

发明人： Toshikazu Nakamura ,  Akira Kikutake ,  Kuninori Kawabata ,  Yasuhiro Onishi ,  Satoshi Eto

IPC分类号： G06F11/00 ,  G11C29/04 ,  G06F11/07

CPC分类号： G11C29/42 ,  G11C11/41

摘要： Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal (in the case shown in FIG. 1, an external upper limit fetch signal) is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.

摘要翻译： 公开了一种半导体存储器件，其能够任意地设定检验动作时的误差修正量的上限。 半导体存储器件具有计数器，寄存器和比较电路。 计数器对错误更正次数进行计数。 当外部输入上限设定信号（在图1所示的情况下为外部上限获取信号）以改变误差修正次数的上限时，该寄存器改变上限值。 比较电路将误差校正次数与改变的上限进行比较。

公开(公告)号：US20090040850A1

公开(公告)日：2009-02-12

申请号：US12130480

申请日：2008-05-30

申请人： Kaoru Mori ,  Toshikazu Nakamura ,  Jun Ohno ,  Masaki Okuda

发明人： Kaoru Mori ,  Toshikazu Nakamura ,  Jun Ohno ,  Masaki Okuda

IPC分类号： G11C29/00 ,  G11C8/00

CPC分类号： G11C8/18 ,  G11C11/401 ,  G11C11/406 ,  G11C11/40615 ,  G11C29/1201 ,  G11C29/18 ,  G11C29/48 ,  G11C2029/1802

摘要： An address switch circuit receives a row address signal supplied to a first address terminal group and a column address signal supplied to a second address terminal group. Further, the address switch circuit receives the row address signal supplied to the second address terminal group and thereafter receives the column address signal supplied to the second address terminal group and supplies the received row address signal and the received column address signal to the row decoder and the column decoder during a second operation mode. The number of semiconductor memories that are tested at once can be increased by executing an operation test of the semiconductor memories in the second operation mode. In addition, it becomes possible to test a semiconductor memory using test assets for other semiconductor memories. Consequently, the test efficiency can be improved, and the test cost can be reduced.

摘要翻译： 地址开关电路接收提供给第一地址端子组的行地址信号和提供给第二地址端子组的列地址信号。 此外，地址开关电路接收提供给第二地址端子组的行地址信号，然后接收提供给第二地址端子组的列地址信号，并将接收到的行地址信号和接收的列地址信号提供给行解码器， 列解码器在第二操作模式期间。 可以通过在第二操作模式下执行半导体存储器的操作测试来增加一次测试的半导体存储器的数量。 此外，可以使用用于其他半导体存储器的测试资产来测试半导体存储器。 因此，可以提高测试效率，并且可以降低测试成本。

公开(公告)号：US07467337B2

公开(公告)日：2008-12-16

申请号：US11102715

申请日：2005-04-11

申请人： Toshikazu Nakamura ,  Akira Kikutake ,  Kuninori Kawabata ,  Yasuhiro Onishi ,  Satoshi Eto

发明人： Toshikazu Nakamura ,  Akira Kikutake ,  Kuninori Kawabata ,  Yasuhiro Onishi ,  Satoshi Eto

IPC分类号： G06F11/00

CPC分类号： G11C29/42 ,  G11C11/41

摘要： Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.

摘要翻译： 公开了一种半导体存储器件，其能够任意地设定检验动作时的误差修正量的上限。 半导体存储器件具有计数器，寄存器和比较电路。 计数器对错误更正次数进行计数。 当外部输入上限设定信号以改变误差修正次数的上限时，寄存器改变上限值。 比较电路将误差校正次数与改变的上限进行比较。

公开(公告)号：US07442331B2

公开(公告)日：2008-10-28

申请号：US11648781

申请日：2007-01-03

申请人： Toshikazu Nakamura

发明人： Toshikazu Nakamura

IPC分类号： B29C47/08

CPC分类号： B29C41/28 ,  B29C41/32 ,  Y10S425/812

摘要： A pipe for supplying a dope to a co-casting die consists of a goose neck portion connected to a feed block of the co-casting die, and a straight pipe portion connected to the goose neck portion. The goose neck portion has a radius of curvature of 50 mm to 400 mm, and the straight pipe portion forms an angle of 0 to 20 degrees to the horizontal plane. Venting valves are opened up at the beginning of dope feeding, and are closed to some extent as the dope comes out. After the air is completely vented out, the venting valves are completely closed. Thereby, an air collection is completely let out from the pipe, a plastic web discharged from die lips of the co-casting die would not contain any air bubbles, it is prevented that the web splashes to put on the die lips, causing streaks on the produced film.

摘要翻译： 用于向共铸铸造模具供应涂料的管由由连接到共铸铸模的进料块的鹅颈部分和连接到鹅颈部的直管部分组成。 鹅颈部具有50mm至400mm的曲率半径，并且直管部分与水平面形成0至20度的角度。 排气阀在涂料开始时打开，当涂料出来时，排气阀在一定程度上关闭。 空气完全排出后，排气阀完全关闭。 因此，空气收集从管道完全排出，从共铸铸模的模唇排出的塑料网不会含有任何气泡，因此可以防止纤维网飞溅地放在模唇上，引起条纹 制作的电影。

公开(公告)号：US20080074943A1

公开(公告)日：2008-03-27

申请号：US11902703

申请日：2007-09-25

申请人： Toshikazu Nakamura ,  Hiroyuki Kobayashi

发明人： Toshikazu Nakamura ,  Hiroyuki Kobayashi

IPC分类号： G11C8/18

CPC分类号： G11C7/22 ,  G11C7/02 ,  G11C7/08 ,  G11C11/4076 ,  G11C11/4091 ,  G11C29/02 ,  G11C29/023 ,  G11C29/026 ,  G11C29/028

摘要： In a semiconductor memory device, in addition to a sense amplifier connected to bit lines of a memory cell array having a plurality of memory cells in a disconnectable manner, the sense amplifier performing confinement operation to disconnect the bit lines of the memory cell array and amplify a data signal during data sense operation from the memory cells, there is provided a timing adjustment circuit adjusting timing related to confinement operation in the sense amplifier, so as to allow adjusting of timing of the confinement operation and setting of timing of the confinement operation.

摘要翻译： 在半导体存储器件中，除了以可断开的方式连接到具有多个存储单元的存储单元阵列的位线的读出放大器之外，读出放大器执行限制操作以断开存储单元阵列的位线并放大 在来自存储器单元的数据读取操作期间的数据信号，提供定时调整电路，调整与读出放大器中的限制操作有关的定时，以便允许调节限制操作的定时和限制操作的定时。