公开(公告)号：US07378900B2

公开(公告)日：2008-05-27

申请号：US11537842

申请日：2006-10-02

申请人： Tomoki Inoue

发明人： Tomoki Inoue

IPC分类号： H03K5/00 ,  H03H7/01

CPC分类号： H03H1/0007 ,  H01L23/552 ,  H01L27/0248 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： EMI filter 20 includes input terminal Vin, output terminal Vout, resistor component R1 and diodes D1 and D2. Resistor component R1 is composed of polycrystalline resistor component Rp and ring resistor components R11 and R12. Polycrystalline resistor component Rp is connected between input and output terminals Vin and Vout. Ring resistor components R11 and R12 are provided on one and the other sides of polycrystalline resistor component at a prescribed distance, respectively. Further, diode D1 has cathode and anode electrodes connected to input terminal Vin and reference potential Vss, respectively. Likewise, diode D2 has cathode and anode electrodes connected to output terminal Vout and reference potential Vss, respectively. Ring resistor components R11 and R12 are rectangular in shape to electromagnetically couple to polycrystalline resistor component Rp. When a high frequency signal is applied to input terminal Vin, an electric current flowing through polycrystalline resistor component Rp generates magnetic fields so that ring resistor components R11 and R12 electro-magnetically induce an electric current.

摘要翻译： EMI滤波器20包括输入端Vin，输出端Vout，电阻分量R 1和二极管D1和D2。 电阻器部件R 1由多晶电阻器部件Rp和环形电阻器部件R 11和R 12构成。 多晶硅电阻元件Rp连接在输入和输出端子Vin和Vout之间。 环状电阻器部件R 11和R 12分别以规定距离设置在多晶电阻器部件的一侧和另一侧上。 此外，二极管D1分别具有连接到输入端Vin和参考电位Vss的阴极和阳极电极。 同样，二极管D 2分别具有连接到输出端Vout和参考电位Vss的阴极和阳极电极。 环形电阻器部件R 11和R 12的形状为矩形，以电磁耦合到多晶电阻器部件Rp。 当向输入端子Vin施加高频信号时，流过多晶硅电阻器部件Rp的电流产生磁场，使得环形电阻器部件R 11和R 12电磁感应出电流。

公开(公告)号：US20070120193A1

公开(公告)日：2007-05-31

申请号：US11563848

申请日：2006-11-28

申请人： Tomoki Inoue

发明人： Tomoki Inoue

IPC分类号： H01L23/62

CPC分类号： H01L27/0255

摘要： An ESD protection device includes: a semiconductor substrate of a first conductivity type having a first major surface and a second major surface; a signal input electrode formed on the first major surface of the semiconductor substrate; a base region of a second conductivity type formed on a surface region of the second major surface of the semiconductor substrate; a diffusion region of the first conductivity type; a resistor layer formed on the second major surface of the semiconductor substrate of the first conductivity type; a signal output electrode electrically connected to the diffusion region of the first conductivity type; and a ground electrode electrically connected to the resistor layer. The diffusion region is selectively formed on a surface region of the base region of the second conductivity type in the semiconductor substrate of the first conductivity type. The resistor layer is electrically connected to the diffusion region of the first conductivity type.

摘要翻译： ESD保护装置包括：具有第一主表面和第二主表面的第一导电类型的半导体衬底; 形成在所述半导体衬底的所述第一主表面上的信号输入电极; 形成在所述半导体衬底的所述第二主表面的表面区域上的第二导电类型的基极区域; 第一导电类型的扩散区; 形成在第一导电类型的半导体衬底的第二主表面上的电阻层; 电连接到第一导电类型的扩散区的信号输出电极; 以及电连接到电阻层的接地电极。 扩散区选择性地形成在第一导电类型的半导体衬底中的第二导电类型的基极区域的表面区域上。 电阻层电连接到第一导电类型的扩散区域。

公开(公告)号：US20060214199A1

公开(公告)日：2006-09-28

申请号：US11369734

申请日：2006-03-08

申请人： Tomoki Inoue ,  Shinji Uya

发明人： Tomoki Inoue ,  Shinji Uya

IPC分类号： H01L31/113

CPC分类号： H01L27/14893 ,  H01L27/14647

摘要： A solid-state image sensing device provided with photoelectric conversion films stacked above a semiconductor substrate, comprising: first impurity regions as defined herein; second impurity regions as defined herein; signal charge reading regions as defined herein; and third impurity regions as defined herein.

摘要翻译： 一种设置在半导体衬底上方的光电转换膜的固态摄像装置，包括：如本文所定义的第一杂质区; 如本文所定义的第二杂质区; 信号电荷读取区域; 和第三杂质区域。

公开(公告)号：US07104571B2

公开(公告)日：2006-09-12

申请号：US10768501

申请日：2004-01-30

申请人： Tomoki Inoue ,  Kazuhito Kasahara

发明人： Tomoki Inoue ,  Kazuhito Kasahara

IPC分类号： F16L35/00

CPC分类号： F16L37/0987 ,  F16L2201/10

摘要： The connector clip for verifying complete connection integrally includes a clip body of U-shape in cross-section to receive a tubular holding portion and a connection verifying portion of U-shape in cross-section to receive an opposite axial side of an annular verification projection with respect to the pipe. The connection verifying portion has a verifying body and a snap-fit portion. The clip body and the verifying body are connected via a connection part, while the verifying body and the snap-fit portion are connected via a joint part. Reinforcement ribs are formed along an entire circumference of outer surface of the verifying body.

摘要翻译： 用于验证完全连接的连接夹一体地包括横截面为U形的夹体，以接收管状保持部分和横截面为U形的连接验证部分，以接收环形验证突起的相对的轴向侧 相对于管道。 连接验证部分具有验证主体和卡扣配合部分。 夹体和验证体经由连接部连接，同时验证体和卡扣配合部经由接合部连接。 加强筋沿着验证体的外表面的整个圆周形成。

公开(公告)号：US06667515B2

公开(公告)日：2003-12-23

申请号：US10053660

申请日：2002-01-24

申请人： Tomoki Inoue

发明人： Tomoki Inoue

IPC分类号： H01L2976

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/7395 ,  H01L29/7802

摘要： A high breakdown voltage semiconductor device includes an active area and a surrounding region. In the active area, a second semiconductor layer of a second conductivity type is formed in a first semiconductor layer of a first conductivity type. A third semiconductor layer of the first conductivity type is formed in the second semiconductor layer. A gate electrode faces through a gate insulating film the second semiconductor layer. A first main electrode is connected to the second and third semiconductor layers. A ring layer of the second conductivity type surrounds the active area at a position in the surrounding region. A first low-resistivity layer is formed in the ring layer and has a resistivity lower than that of the ring layer. The first low-resistivity layer is connected to the first main electrode.

公开(公告)号：US06290264B1

公开(公告)日：2001-09-18

申请号：US09791709

申请日：2001-02-26

申请人： Tomoki Inoue

发明人： Tomoki Inoue

IPC分类号： F16L3500

CPC分类号： F16L37/0987 ,  F16L3/02 ,  Y10S285/921

摘要： A resin tube 9 inserted and fixed to one end of a female connector 10 and a corresponding pipe 11 connected by snap in to the other end of a female connector 10 are fixed by a first holding means 17 and a second holding means 18 of a holder member 16 respectively. Holding portion of either the resin tube 9 and the corresponding pipe 11 is located off the common axis L as securely held by the holder member 16. Either the resin tube 9 or the corresponding pipe 11 is turned about the female connector 10 so as to connect with either the first holding means 17 or the second holding means 18.

摘要翻译： 插入并固定到阴连接器10的一端的树脂管9和通过卡入阴连接器10的另一端连接的相应管11由第一保持装置17和保持器的第二保持装置18固定 成员16。 树脂管9和相应管11的保持部分位于由保持件16牢固地保持的公共轴线L之外。树脂管9或相应的管11都绕阴连接器10转动以便连接 第一保持装置17或第二保持装置18。

公开(公告)号：US6037632A

公开(公告)日：2000-03-14

申请号：US744212

申请日：1996-11-05

申请人： Ichiro Omura ,  Tomoki Inoue ,  Hiromichi Ohashi

发明人： Ichiro Omura ,  Tomoki Inoue ,  Hiromichi Ohashi

IPC分类号： H01L21/336 ,  H01L21/74 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/70 ,  H01L29/739 ,  H01L29/78 ,  H01L29/872 ,  H01L29/74 ,  H01L23/58 ,  H01L29/76

CPC分类号： H01L29/7816 ,  H01L21/74 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/404 ,  H01L29/405 ,  H01L29/66712 ,  H01L29/739 ,  H01L29/7395 ,  H01L29/7801 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/872 ,  H01L29/41775 ,  H01L2924/0002

摘要： A semiconductor device is disclosed, which comprises a first main electrode, a second main electrode, a high-resistance semiconductor layer of first conductivity type interposed between the first main electrode and the second main electrode, and at least a buried layer of second conductivity type selectively formed in the semiconductor layer, extending at substantially right angles to a line connecting the first and second main electrodes, comprising a plurality strips functioning as current paths and set at a potential different from a potential of any other electrode when a depletion layer extending from a region near the first main electrode reaches the buried layer.

摘要翻译： 公开了一种半导体器件，其包括第一主电极，第二主电极，插入在第一主电极和第二主电极之间的第一导电类型的高电阻半导体层，以及至少第二导电类型的掩埋层 选择性地形成在半导体层中，以与连接第一和第二主电极的线基本成直角延伸，包括用作电流路径的多个条带，并且当从第一和第二主电极延伸的耗尽层设置为与任何其它电极的电位不同的电位时 第一主电极附近的区域到达掩埋层。

公开(公告)号：US5838026A

公开(公告)日：1998-11-17

申请号：US827530

申请日：1997-03-28

申请人： Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoki Inoue

发明人： Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoki Inoue

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L29/745 ,  H01L21/36

CPC分类号： H01L29/7455 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7398 ,  H01L29/0696 ,  H01L29/4236

摘要： An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.

摘要翻译： 绝缘栅半导体器件包括P型发射极层，形成在P型发射极层上的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。 形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。 覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。 在一些沟槽之间的沟道区域中，在P型基极层的表面形成有与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。 连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。

公开(公告)号：US5585651A

公开(公告)日：1996-12-17

申请号：US487508

申请日：1995-06-07

申请人： Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoki Inoue

发明人： Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoki Inoue

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L29/745 ,  H01L29/74 ,  H01L31/111

CPC分类号： H01L29/7455 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7398 ,  H01L29/0696 ,  H01L29/4236

摘要： An insulated-gate semiconductor device comprises a p type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.

摘要翻译： 绝缘栅半导体器件包括p型发射极层，在P型发射极层上形成的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。 形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。 覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。 在一些沟槽之间的沟道区域中，在P型基极层的表面形成有与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。 连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。

公开(公告)号：US5448083A

公开(公告)日：1995-09-05

申请号：US261384

申请日：1994-06-15

申请人： Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoki Inoue

发明人： Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa ,  Norio Yasuhara ,  Tomoki Inoue

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L29/745 ,  H01L21/36 ,  H01L21/74

CPC分类号： H01L29/7455 ,  H01L29/7394 ,  H01L29/7397 ,  H01L29/7398 ,  H01L29/0696 ,  H01L29/4236

摘要： An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby-forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.

摘要翻译： 绝缘栅半导体器件包括P型发射极层，形成在P型发射极层上的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。 形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。 覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。 在一些沟槽之间的沟道区域中，在P型基极层的表面上形成与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。 连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。