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公开(公告)号：US5689121A
公开(公告)日：1997-11-18
申请号：US480389
申请日：1995-06-07
IPC分类号： H01L29/06 , H01L29/423 , H01L29/739 , H01L29/745 , H01L29/74 , H01L31/111
CPC分类号： H01L29/7455 , H01L29/7394 , H01L29/7397 , H01L29/7398 , H01L29/0696 , H01L29/4236
摘要： An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.
摘要翻译： 绝缘栅半导体器件包括P型发射极层，形成在P型发射极层上的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。 形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。 覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。 在一些沟槽之间的沟道区域中，在P型基极层的表面形成有与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。 连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。
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公开(公告)号：US5838026A
公开(公告)日：1998-11-17
申请号：US827530
申请日：1997-03-28
IPC分类号： H01L29/06 , H01L29/423 , H01L29/739 , H01L29/745 , H01L21/36
CPC分类号： H01L29/7455 , H01L29/7394 , H01L29/7397 , H01L29/7398 , H01L29/0696 , H01L29/4236
摘要： An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.
摘要翻译： 绝缘栅半导体器件包括P型发射极层，形成在P型发射极层上的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。 形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。 覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。 在一些沟槽之间的沟道区域中，在P型基极层的表面形成有与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。 连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。
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公开(公告)号：US5585651A
公开(公告)日：1996-12-17
申请号：US487508
申请日：1995-06-07
IPC分类号： H01L29/06 , H01L29/423 , H01L29/739 , H01L29/745 , H01L29/74 , H01L31/111
CPC分类号： H01L29/7455 , H01L29/7394 , H01L29/7397 , H01L29/7398 , H01L29/0696 , H01L29/4236
摘要： An insulated-gate semiconductor device comprises a p type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.
摘要翻译： 绝缘栅半导体器件包括p型发射极层，在P型发射极层上形成的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。 形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。 覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。 在一些沟槽之间的沟道区域中，在P型基极层的表面形成有与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。 连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。
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公开(公告)号：US5448083A
公开(公告)日：1995-09-05
申请号：US261384
申请日：1994-06-15
IPC分类号： H01L29/06 , H01L29/423 , H01L29/739 , H01L29/745 , H01L21/36 , H01L21/74
CPC分类号： H01L29/7455 , H01L29/7394 , H01L29/7397 , H01L29/7398 , H01L29/0696 , H01L29/4236
摘要： An insulated-gate semiconductor device comprises a P type emitter layer, an N.sup.- high-resistive base layer formed on the P type emitter layer, and a P type base layer contacting the N.sup.- high-resistive base layer. A plurality of trenches are formed having a depth to reach into the N.sup.- high-resistive base layer from the P type base layer. A gate electrode covered with a gate insulation film is buried in each trench. An N type source layer to be connected to a cathode electrode is formed in the surface of the P type base layer in a channel region between some trenches, thereby-forming an N channel MOS transistor for turn-on operation. A P channel MOS transistor connected to the P base layer is formed in a channel region between other trenches so as to discharge the holes outside the device upon turn-off operation.
摘要翻译： 绝缘栅半导体器件包括P型发射极层，形成在P型发射极层上的N-高电阻基极层和与N型高电阻基极层接触的P型基极层。 形成从P型基底层到达N个高电阻基底层的深度的多个沟槽。 覆盖有栅极绝缘膜的栅电极被埋在每个沟槽中。 在一些沟槽之间的沟道区域中，在P型基极层的表面上形成与阴极连接的N型源极层，从而形成用于导通工作的N沟道MOS晶体管。 连接到P基极层的P沟道MOS晶体管形成在其它沟槽之间的沟道区域中，以便在关断操作时将器件的孔排出。
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公开(公告)号：US6069371A
公开(公告)日：2000-05-30
申请号：US39383
申请日：1998-03-16
申请人： Ichiro Omura , Tomoki Inoue
发明人： Ichiro Omura , Tomoki Inoue
IPC分类号： H01L29/78 , H01L27/08 , H01L29/739 , H01L29/861 , H01L29/87
CPC分类号： H01L27/0817 , H01L27/0814 , H01L29/7395 , H01L29/861
摘要： A semiconductor rectifier in which the sum of loss during reverse recovery and loss in a conducting state can be suppressed even if the ratio between the periods of the conducting and blocking states varies and a method of driving the same are disclosed. A voltage is applied to a gate electrode formed in a face-to-face relationship with a base layer of a first conductivity type and an emitter layer of a second conductivity type with a gate insulation film interposed therebetween to form an inversion layer on the surface of the base layer of the first conductivity type. As a result, the base layer of the first conductivity type and the short layer of the first conductivity type are short-circuited to decrease the density of carriers in the base layer of the first conductivity type, loss during a reverse recovery operation can be suppressed.
摘要翻译： 即使在导通和阻塞状态的周期之间的比率发生变化的情况下也能够抑制反向恢复中的损耗和导通状态的损耗之和的半导体整流器及其驱动方法。 将电压施加到与第一导电类型的基极层和第二导电类型的发射极层的面对面关系形成的栅电极，其间插入栅极绝缘膜，以在表面上形成反型层 的第一导电类型的基层。 结果，第一导电类型的基层和第一导电类型的短层被短路以降低第一导电类型的基极层中的载流子的密度，可以抑制反向恢复操作期间的损耗 。
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公开(公告)号：US07078740B2
公开(公告)日：2006-07-18
申请号：US10843571
申请日：2004-05-12
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L29/0696 , H01L29/0619 , H01L29/0839 , H01L29/407 , H01L29/4236 , H01L29/66348 , H01L29/7394 , H01L29/7395 , H01L29/7397
摘要： A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.
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公开(公告)号：US06137136A
公开(公告)日：2000-10-24
申请号：US932464
申请日：1997-09-18
申请人： Akihiro Yahata , Satoshi Urano , Tomoki Inoue , Ichiro Omura
发明人： Akihiro Yahata , Satoshi Urano , Tomoki Inoue , Ichiro Omura
IPC分类号： H01L29/74 , H01L21/336 , H01L29/06 , H01L29/423 , H01L29/739 , H01L29/749 , H01L29/78 , H01L29/76
CPC分类号： H01L29/0696 , H01L29/7397 , H01L29/4236
摘要： An injection enhanced insulated gate bipolar transistor is disclosed in which an average roughness of silicon on the side and bottom surfaces of trench grooves below a gate oxide film is made to be 0.6 nm or smaller. Irregular portions on the surface of silicon of the gate oxide film can be prevented. Thus, lowering of the gate breakdown voltage occurring because of dispersion of the thickness of the gate oxide film due to the irregular portions can be prevented.
摘要翻译： 公开了一种注入增强型绝缘栅双极型晶体管，其中在栅极氧化膜下方的沟槽槽的侧表面和底表面上的平均粗糙度为0.6nm或更小。 可以防止栅极氧化膜的硅表面上的不规则部分。 因此，可以防止由于不规则部分导致的栅极氧化膜的厚度的分散而产生的栅极击穿电压的降低。
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公开(公告)号：US5714775A
公开(公告)日：1998-02-03
申请号：US633688
申请日：1996-04-19
申请人： Tomoki Inoue , Ichiro Omura , Hiromichi Ohashi
发明人： Tomoki Inoue , Ichiro Omura , Hiromichi Ohashi
IPC分类号： H01L29/06 , H01L29/10 , H01L29/32 , H01L29/739 , H01L29/74 , H01L31/111
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/1095 , H01L29/32
摘要： A p-type emitter layer having a low resistivity is arranged on a bottom surface of an n-type base layer having a high resistivity. A p-type base layer is formed in a top surface of the n-type base layer. Trenches are formed in the p-type base layer and the n-type base layer such that each trench penetrates the p-type base layer and reaches down to a halfway depth in the n-type base layer. Inter-trench regions made of semiconductor are defined between the trenches. An n-type emitter layer having a low resistivity is formed in a surface of the p-type base layer to be in contact with the upper part of each trench. A gate electrode is buried via a gate insulating film in each trench. That side surface of each inter-trench region which faces the gate electrode consists of a {100} plane.
摘要翻译： 具有低电阻率的p型发射极层布置在具有高电阻率的n型基极层的底表面上。 p型基底层形成在n型基底层的顶表面上。 在p型基底层和n型基底层中形成沟槽，使得每个沟槽穿过p型基底层并在n型基底层中下降到中间深度。 在沟槽之间限定由半导体制成的沟槽间区域。 在p型基底层的表面上形成具有低电阻率的n型发射极层，以与每个沟槽的上部接触。 每个沟槽中的栅极绝缘膜埋入栅电极。 面对栅电极的每个沟槽间区域的侧表面由{100}平面组成。
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公开(公告)号：US20060006409A1
公开(公告)日：2006-01-12
申请号：US11221702
申请日：2005-09-09
IPC分类号： H01L29/423
CPC分类号： H01L29/0696 , H01L29/0619 , H01L29/0839 , H01L29/407 , H01L29/4236 , H01L29/66348 , H01L29/7394 , H01L29/7395 , H01L29/7397
摘要： A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.
摘要翻译： 功率半导体器件包括在距离第二导电类型的集电极层的位置处间隔设置在第一导电类型的第一基极层中的沟槽，以分隔主单元和虚设单元。 在主电池中，设置第二导电类型的第二基极层和第一导电类型的发射极层。 在虚拟电池中设置第二导电类型的缓冲层。 栅电极通过栅极绝缘膜设置在与主电池相邻的沟槽中。 具有无限大电阻值的缓冲电阻器插入在缓冲层和发射极之间。 虚设电池具有抑制结构，以减少第二导电类型的载流子从集电极层流入和积聚在缓冲层中。
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公开(公告)号：US07170106B2
公开(公告)日：2007-01-30
申请号：US11221702
申请日：2005-09-09
IPC分类号： H01L29/74 , H01L29/423 , H01L31/111
CPC分类号： H01L29/0696 , H01L29/0619 , H01L29/0839 , H01L29/407 , H01L29/4236 , H01L29/66348 , H01L29/7394 , H01L29/7395 , H01L29/7397
摘要： A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.
摘要翻译： 功率半导体器件包括在距离第二导电类型的集电极层的位置处间隔设置在第一导电类型的第一基极层中的沟槽，以分隔主单元和虚设单元。 在主电池中，设置第二导电类型的第二基极层和第一导电类型的发射极层。 在虚拟电池中设置第二导电类型的缓冲层。 栅电极通过栅极绝缘膜设置在与主电池相邻的沟槽中。 具有无限大电阻值的缓冲电阻器插入在缓冲层和发射极之间。 虚设电池具有抑制结构，以减少第二导电类型的载流子从集电极层流入和积聚在缓冲层中。
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