公开(公告)号：US10929234B2

公开(公告)日：2021-02-23

申请号：US15881480

申请日：2018-01-26

Applicant: VMware, Inc.

Inventor： Kiran Tati ,  Qasim Ali ,  Wei Xu ,  Rajesh Venkatasubramanian ,  Pratap Subrahmanyam

IPC: G06F11/14 ,  G06F16/27 ,  G06F1/26 ,  G06F11/20

Abstract: Techniques for implementing application fault tolerance via battery-backed replication of volatile state are provided. In one set of embodiments, a primary host system can detect a failure that causes an application of the primary host system to stop running. In response to detecting the failure, the primary host system can replicate volatile state that is used by the application to a secondary host system, where the secondary host system maintains a copy of the application, and where execution of the application is failed over to the copy on the secondary host system using the replicated volatile state.

公开(公告)号：US20210019168A1

公开(公告)日：2021-01-21

申请号：US16698994

申请日：2019-11-28

Applicant: VMWARE, INC.

Inventor： Marcos Aguilera ,  Keerthi Kumar ,  Pramod Kumar ,  Arun Ramanathan ,  Pratap Subrahmanyam ,  Sairam Veeraswamy ,  Rajesh Venkatasubramanian ,  Manish Mishra

IPC: G06F9/455 ,  G06F3/06 ,  G06F12/1009 ,  G06F16/907

Abstract: The disclosure provides an approach for creating a pool of memory out of local memories of host machines, and providing that pool for the hosts to use. The pool is managed by a controller that keeps track of memory usage and allocated memory among hosts. The controller allocates or reclaims memory between hosts, as needed by the hosts. Memory allocated from a second host to a first host may then be divided into smaller portions by the first host, and further allocated to virtual machines executing within the first host.

公开(公告)号：US20200133846A1

公开(公告)日：2020-04-30

申请号：US16174264

申请日：2018-10-29

Applicant: VMware, Inc.

Inventor： Kiran Tati ,  Xavier Deguillard ,  Ishan Banerjee ,  Julien Freche ,  Preeti Agarwal ,  Rajesh Venkatasubramanian

IPC: G06F12/02 ,  G06F12/0804

Abstract: Techniques for efficiently purging non-active blocks in an NVM region of an NVM device using pointer elimination are provided. In one set of embodiments, a host system can, for each level 1 (L1) page table entry of each snapshot of the NVM region, determine whether a data block of the NVM region that is pointed to by the L1 page table entry is a non-active block, and if the data block is a non-active block, remove a pointer to the data block in the L1 page table entry and reduce a reference count parameter associated with the data block by 1. If the reference count parameter has reached zero at this point, the host system purge the data block from the NVM device to the mass storage device.

公开(公告)号：US10528436B2

公开(公告)日：2020-01-07

申请号：US15192940

申请日：2016-06-24

Applicant: VMware, Inc.

Inventor： Pratap Subrahmanyam ,  Zongwei Zhou ,  Xavier Deguillard ,  Rajesh Venkatasubramanian

IPC: G06F16/30 ,  G06F11/14 ,  G06F16/23

Abstract: Techniques for using micro-journals to ensure crash consistency of a transactional application are provided. In one embodiment, a computer system can receive a transaction associated with the transactional application, where the transaction includes a plurality of modifications to data or metadata of the transactional application. The computer system can further select a free micro-journal from a pool of micro-journals, where the pool of micro-journals are stored in a byte-addressable persistent memory of the computer system, and where each micro-journal in the pool is configured to record journal entries for a single transaction at a time. The computer system can then write journal entries into the micro-journal corresponding to the plurality of modifications included in the transaction and commit the journal entries to the byte-addressable persistent memory.

公开(公告)号：US20200004735A1

公开(公告)日：2020-01-02

申请号：US16560951

申请日：2019-09-04

Applicant: VMware, Inc.

Inventor： Pratap Subrahmanyam ,  Zongwei Zhou ,  Xavier Deguillard ,  Rajesh Venkatasubramanian

IPC: G06F16/23

Abstract: Techniques for using commit coalescing when performing micro-journal-based transaction logging are provided. In one embodiment a computer system can maintain, in a volatile memory, a globally ascending identifier, a first list of free micro-journals, and a second list of in-flight micro-journals. The computer system can further receive a transaction comprising a plurality of modifications to data or metadata stored in the byte-addressable persistent memory, select a micro-journal from the first list, obtain a lock on the globally ascending identifier, write a current value of the globally ascending identifier as a journal commit identifier into a header of the micro-journal, and write journal entries into the micro-journal corresponding to the plurality of modifications included in the transaction. The computer system can then commit the micro-journal to the byte-addressable persistent memory, increment the current value of the globally ascending identifier, and release the lock.

公开(公告)号：US20190171390A1

公开(公告)日：2019-06-06

申请号：US15830850

申请日：2017-12-04

Applicant: VMware, Inc.

Inventor： Julien Freche ,  Kiran Tati ,  Rajesh Venkatasubramanian

IPC: G06F3/06

Abstract: Hierarchical resource tree memory operations can include receiving, at a memory scheduler, an indication of a proposed modification to a value of a memory parameter of an object represented by a node of a hierarchical resource tree, wherein the proposed modification is made by a modifying entity, locking the node of the hierarchical resource tree by the memory scheduler, performing the proposed modification by the memory scheduler, wherein performing the proposed modification includes creating a working value of the memory parameter according to the proposed modification, determining whether the proposed modification violates a structural consistency of the hierarchical resource tree based on the working value, and replacing the value of the memory parameter with the working value of the memory parameter in response to determining that the proposed modification does not violate a structural consistency of the hierarchical resource tree based on the working value, and unlocking the node of the hierarchical resource tree by the memory scheduler.

公开(公告)号：US20180322023A1

公开(公告)日：2018-11-08

申请号：US15586020

申请日：2017-05-03

Applicant: VMware, Inc.

Inventor： Pratap Subrahmanyam ,  Rajesh Venkatasubramanian ,  Kiran Tati ,  Qasim Ali

IPC: G06F11/20 ,  G06F12/0804

Abstract: Techniques for implementing high availability for persistent memory are provided. In one embodiment, a first computer system can detect an alternating current (AC) power loss/cycle event and, in response to the event, can save data in a persistent memory of the first computer system to a memory or storage device that is remote from the first computer system and is accessible by a second computer system. The first computer system can then generate a signal for the second computer system subsequently to initiating or completing the save process, thereby allowing the second computer system to restore the saved data from the memory or storage device into its own persistent memory.

公开(公告)号：US20180321962A1

公开(公告)日：2018-11-08

申请号：US15586109

申请日：2017-05-03

Applicant: VMware, Inc.

Inventor： Venkata Subhash Reddy Peddamallu ,  Kiran Tati ,  Rajesh Venkatasubramanian ,  Pratap Subrahmanyam

IPC: G06F9/455 ,  G06F3/06 ,  G06F9/50

CPC classification number: G06F9/45558 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/0685 ,  G06F9/5016 ,  G06F2009/45579 ,  G06F2009/45583

Abstract: Techniques for implementing OS/hypervisor-based persistent memory are provided. In one embodiment, an OS or hypervisor running on a computer system can allocate a portion of the volatile memory of the computer system as a persistent memory allocation. The OS/hypervisor can further receive a signal from the computer system's BIOS indicating an AC power loss or cycle event and, in response to the signal, can save data in the persistent memory allocation to a nonvolatile backing store. Then, upon restoration of AC power to the computer system, the OS/hypervisor can restore the saved data from the nonvolatile backing store to the persistent memory allocation.

公开(公告)号：US09977738B2

公开(公告)日：2018-05-22

申请号：US15289893

申请日：2016-10-10

Applicant: VMware, Inc.

Inventor： Rajesh Venkatasubramanian ,  Puneet Zaroo ,  Alexandre Milouchev

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/0891 ,  G06F9/50 ,  G06F9/455 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/1009 ,  G06F3/06 ,  G06F12/06 ,  G06F12/02 ,  G06F12/1072 ,  G06F12/0868 ,  G06F12/10

CPC classification number: G06F12/08 ,  G06F3/0604 ,  G06F3/0614 ,  G06F3/0662 ,  G06F3/0665 ,  G06F9/45558 ,  G06F9/5033 ,  G06F9/5083 ,  G06F12/0292 ,  G06F12/0638 ,  G06F12/0811 ,  G06F12/084 ,  G06F12/0868 ,  G06F12/0891 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1072 ,  G06F2009/45583 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/2542 ,  G06F2212/6042 ,  G06F2212/62

Abstract: In a system having non-uniform memory access architecture, with a plurality of nodes, memory access by entities such as virtual CPUs is estimated by invalidating a selected sub-set of memory units, and then detecting and compiling access statistics, for example by counting the page faults that arise when any virtual CPU accesses an invalidated memory unit. The entities, or pairs of entities, may then be migrated or otherwise co-located on the node for which they have greatest memory locality.

公开(公告)号：US20170344440A1

公开(公告)日：2017-11-30

申请号：US15192940

申请日：2016-06-24

Applicant: VMware, Inc.

Inventor： Pratap Subrahmanyam ,  Zongwei Zhou ,  Xavier Deguillard ,  Rajesh Venkatasubramanian

IPC: G06F11/14 ,  G06F17/30

Abstract: Techniques for using micro-journals to ensure crash consistency of a transactional application are provided. In one embodiment, a computer system can receive a transaction associated with the transactional application, where the transaction includes a plurality of modifications to data or metadata of the transactional application. The computer system can further select a free micro-journal from a pool of micro-journals, where the pool of micro-journals are stored in a byte-addressable persistent memory of the computer system, and where each micro-journal in the pool is configured to record journal entries for a single transaction at a time. The computer system can then write journal entries into the micro-journal corresponding to the plurality of modifications included in the transaction and commit the journal entries to the byte-addressable persistent memory.