公开(公告)号：US6077402A

公开(公告)日：2000-06-20

申请号：US857719

申请日：1997-05-16

申请人： Liubo Hong ,  Hougong Wang ,  Gongda Yao ,  Zheng Xu

发明人： Liubo Hong ,  Hougong Wang ,  Gongda Yao ,  Zheng Xu

IPC分类号： H05H1/46 ,  C23C14/34 ,  C23C14/40 ,  H01J37/32 ,  H01J37/34 ,  H01L21/203 ,  H01L21/285

CPC分类号： H01J37/321 ,  H01J37/34 ,  H01J2237/3323

摘要： In a plasma generating apparatus, a coil is positioned between a target and a workpiece to inductively couple RF energy into a plasma so that the paths of a portion of the ionized deposition material are deflected from the center of the workpiece and toward the edges of the workpiece. As a consequence, it has been found that the uniformity of deposition may be improved. In the illustrated embodiment, the coil is a multi-turn coil formed in a generally planar spiral centered in the stream of deposition material.

摘要翻译： 在等离子体发生装置中，线圈位于靶和工件之间，以将RF能量感应耦合到等离子体中，使得电离沉积材料的一部分的路径从工件的中心偏转并且朝向工件的边缘 工件。 因此，已经发现可以提高沉积的均匀性。 在所示实施例中，线圈是形成在沉积材料流中心的大致平面螺旋形的多匝线圈。

公开(公告)号：US08422276B2

公开(公告)日：2013-04-16

申请号：US12930955

申请日：2011-01-20

申请人： Jun Yuan ,  Liubo Hong ,  Mao-Min Chen

发明人： Jun Yuan ,  Liubo Hong ,  Mao-Min Chen

IPC分类号： G11C11/00

CPC分类号： H01L43/12 ,  H01L27/222 ,  H01L43/08

摘要： Methods are presented for fabricating an MTJ element having a uniform vertical distance between its free layer and a bit line and, in addition, having a protective spacer layer formed abutting the lateral sides of the MTJ element to eliminate leakage currents between MTJ layers and the bit line. Each method forms a dielectric spacer layer on the lateral sides of the MTJ element and, depending on the method, includes an additional layer that protects the spacer layer during etching processes used to form a Cu damascene bit line. At various stages in the process, a dielectric layer is also formed to act as a CMP stop layer so that the capping layer on the MTJ element is not thinned by the CMP process that planarizes the surrounding insulation. Subsequent to planarization, the stop layer is removed by an anisotropic etch of such precision that the MTJ element capping layer is not reduced in thickness and serves to maintain uniform vertical distance between the bit line and the MTJ free layer.

摘要翻译： 提出了用于制造在其自由层和位线之间具有均匀垂直距离的MTJ元件的方法，此外，具有邻接MTJ元件的侧面形成的保护间隔层，以消除MTJ层与钻头之间的泄漏电流 线。 每种方法在MTJ元件的侧面上形成电介质间隔层，并且根据该方法，包括在用于形成Cu镶嵌位线的蚀刻工艺期间保护间隔层的附加层。 在该过程的各个阶段，还形成介电层以用作CMP停止层，使得MTJ元件上的覆盖层不会通过使周围绝缘平坦化的CMP工艺变薄。 在平坦化之后，通过各向异性蚀刻去除停止层，其精度使得MTJ元件覆盖层的厚度不减小并用于保持位线和MTJ自由层之间的均匀垂直距离。

公开(公告)号：US20110089140A1

公开(公告)日：2011-04-21

申请号：US12581042

申请日：2009-10-16

申请人： Liubo Hong

发明人： Liubo Hong

IPC分类号： B44C1/22

CPC分类号： B82Y25/00 ,  B82Y10/00 ,  G01R33/098 ,  G11B5/3116 ,  G11B5/3163 ,  G11B5/3909 ,  G11B2005/3996

摘要： A method for manufacturing a magnetoresistive sensor at very small dimensions with well a controlled track width and clean damage free side wall junctions. The method uses nano-imprinting rather than photolithography to pattern a resist layer. This eliminates the track width variations inherent in photolithographic patterning. The use of nano-imprinting also eliminates the need for a bottom anti-reflective coating beneath the resist layer, thereby also eliminating the need for an additional etch process to remove the bottom anti-reflective coating, which would also cause variations in track width.

摘要翻译： 一种在非常小的尺寸制造磁阻传感器的方法，具有受控的轨道宽度和清洁的无损坏的侧壁接合点。 该方法使用纳米压印而不是光刻来图案化抗蚀剂层。 这消除了光刻图案中固有的轨道宽度变化。 使用纳米压印也消除了在抗蚀剂层下面的底部抗反射涂层的需要，从而也不需要额外的蚀刻工艺去除底部抗反射涂层，这也会导致轨道宽度的变化。

公开(公告)号：US20110089139A1

公开(公告)日：2011-04-21

申请号：US12581030

申请日：2009-10-16

申请人： Liubo Hong

发明人： Liubo Hong

IPC分类号： B44C1/22

CPC分类号： B82Y10/00 ,  B82Y25/00 ,  G01R33/098 ,  G11B5/3116 ,  G11B5/3163 ,  G11B5/3909 ,  G11B2005/3996

摘要： A method for manufacturing a magnetoresistive read sensor that allows the sensor to be constructed with clean well defined side junctions, even at very narrow track widths. The method involves using first and second etch mask layers, that are constructed of materials such that the second mask (formed over the first mask) can act as a mask during the patterning of the first mask (bottom mask). The first mask has a well defined thickness that is defined by deposition and which is not affected by the etching processes used to define the mask. This allows the total ion milling etch mask thickness to be well controlled before the ion milling process used to define the sensor side walls.

摘要翻译： 一种用于制造磁阻读取传感器的方法，即使在非常窄的轨道宽度下也能够使传感器构造成具有清晰良好定义的侧面接合点。 该方法包括使用由材料构成的第一和第二蚀刻掩模层，使得第二掩模（形成在第一掩模上）可以在图案化第一掩模（底掩模）期间用作掩模。 第一掩模具有由沉积限定的良好限定的厚度，并且其不受用于限定掩模的蚀刻工艺的影响。 这允许在用于限定传感器侧壁的离子铣削过程之前，完全控制总离子铣削蚀刻掩模厚度。

公开(公告)号：US07449345B2

公开(公告)日：2008-11-11

申请号：US10868715

申请日：2004-06-15

申请人： Cheng T. Horng ,  Ru-Ying Tong ,  Liubo Hong ,  Min Li

发明人： Cheng T. Horng ,  Ru-Ying Tong ,  Liubo Hong ,  Min Li

IPC分类号： G11B5/72 ,  H01L41/06

CPC分类号： H01L43/08 ,  B82Y10/00 ,  B82Y25/00 ,  G11B5/3906 ,  G11B5/3909 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  H01L43/10 ,  H01L43/12

摘要： An MTJ in an MRAM array or in a TMR read head is comprised of a capping layer with a lower inter-diffusion barrier layer, an intermediate oxygen gettering layer, and an upper metal layer that contacts a top conductor. The composite capping layer is especially useful with a moderate spin polarization free layer such as a NiFe layer with a Fe content of about 17.5 to 20 atomic %. The capping layer preferably has a Ru/Ta/Ru configuration in which the lower Ru layer is about 10 to 30 Angstroms thick and the Ta layer is about 30 Angstroms thick. As a result, a high dR/R of about 40% is achieved with low magnetostriction less than about 1.0 E−6 in an MTJ in an MRAM array. Best results are obtained with an AlOx tunnel barrier layer formed by an in-situ ROX process on an 8 to 10 Angstrom thick Al layer.

摘要翻译： MRAM阵列或TMR读取头中的MTJ由具有较低的互扩散阻挡层的覆盖层，中间氧吸气层和接触顶部导体的上部金属层组成。 复合覆盖层特别适用于中等自旋极化自由层，例如Fe含量约为17.5至20原子％的NiFe层。 封端层优选具有Ru / Ta / Ru构型，其中下Ru层的厚度约为10至30埃，Ta层约为30埃厚。 结果，在MRAM阵列的MTJ中，具有约40％的高dR / R达到小于约1.0E-6的低磁致伸缩。 通过在8至10埃厚的Al层上通过原位ROX工艺形成的AlOx隧道势垒层获得最佳结果。

公开(公告)号：US07335960B2

公开(公告)日：2008-02-26

申请号：US11179252

申请日：2005-07-12

申请人： Cherng-Chyi Han ,  Liubo Hong

发明人： Cherng-Chyi Han ,  Liubo Hong

IPC分类号： H01L43/00

CPC分类号： H01L27/222 ,  H01L43/12

摘要： A method for forming MRAM cell structures wherein the topography of the cell is substantially flat and the distance between a bit line and a magnetic free layer, a word line and a magnetic free layer or a word line and a bit line and a magnetic free layer is precise and well controlled. The method includes the formation of an MTJ film stack over which is formed both a capping and sacrificial layer. The stack is patterned by conventional means, then is covered by a layer of insulation which is thinned by CMP to expose a remaining portion of the sacrificial layer. The remaining portion of the sacrificial layer can be precisely removed by an etching process, leaving only the well dimensioned capping layer to separate the bit line from the magnetic free layer and the capping layer. The bit line and an intervening layer of insulation separate the free layer from a word line in an equally precise and controlled manner.

摘要翻译： 一种用于形成MRAM单元结构的方法，其中单元的形貌基本上是平坦的，并且位线和无磁性层，字线和无磁性层或字线以及位线和无磁层之间的距离 是精确和良好的控制。 该方法包括形成MTJ膜堆叠，在其上形成封盖层和牺牲层。 堆叠通过常规方式图案化，然后被由CMP稀疏以暴露牺牲层的剩余部分的绝缘层覆盖。 可以通过蚀刻工艺精确地去除牺牲层的剩余部分，仅留下孔尺寸的覆盖层以将位线与无磁性层和封盖层分离。 位线和绝缘层的绝缘层以同样精确和受控的方式将自由层与字线分开。

公开(公告)号：US20070281427A1

公开(公告)日：2007-12-06

申请号：US11891923

申请日：2007-08-14

申请人： Wei Cao ,  Chyu-Jiuh Torng ,  Cheng Horng ,  Ruying Tong ,  Chen-Jung Chien ,  Liubo Hong

发明人： Wei Cao ,  Chyu-Jiuh Torng ,  Cheng Horng ,  Ruying Tong ,  Chen-Jung Chien ,  Liubo Hong

IPC分类号： H01L21/336

CPC分类号： H01L43/12 ,  H01L27/228

摘要： A method to fabricate an MTJ device and its connections to a CMOS integrated circuit is described. The device is built out of three layers. The bottom layer serves as a seed layer for the center layer, which is alpha tantalum, while the third, topmost, layer is selected for its smoothness, its compatibility with the inter-layer dielectric materials, and its ability to protect the underlying tantalum.

摘要翻译： 描述了制造MTJ器件及其与CMOS集成电路的连接的方法。 该设备由三层构建。 底层用作中心层的种子层，其为α钽，而第三最顶层选择为其平滑度，其与层间电介质材料的相容性以及其保护下面的钽的能力。

公开(公告)号：US07265404B2

公开(公告)日：2007-09-04

申请号：US11215276

申请日：2005-08-30

申请人： Wei Cao ,  Chyu-Jiuh Torng ,  Cheng Horng ,  Ruying Tong ,  Chen-Jung Chien ,  Liubo Hong

发明人： Wei Cao ,  Chyu-Jiuh Torng ,  Cheng Horng ,  Ruying Tong ,  Chen-Jung Chien ,  Liubo Hong

IPC分类号： H01L29/76

CPC分类号： H01L43/12 ,  H01L27/228

摘要： A structure that is well suited to connecting an MTJ device to a CMOS integrated circuit is described. It is built out of three layers. The bottom layer serves as a seed layer for the center layer, which is alpha tantalum, while the third, topmost, layer is selected for its smoothness, its compatibility with the inter-layer dielectric materials, and its ability to protect the underlying tantalum. A method for its formation is also described.

摘要翻译： 描述了非常适合于将MTJ设备连接到CMOS集成电路的结构。 它由三层构建。 底层用作中心层的种子层，其为α钽，而第三最顶层选择为其平滑度，其与层间电介质材料的相容性以及其保护下面的钽的能力。 还描述了其形成方法。

公开(公告)号：US07211447B2

公开(公告)日：2007-05-01

申请号：US11080868

申请日：2005-03-15

申请人： Cheng T. Horng ,  Ru-Ying Tong ,  Mao-Min Chen ,  Liubo Hong ,  Min Li

发明人： Cheng T. Horng ,  Ru-Ying Tong ,  Mao-Min Chen ,  Liubo Hong ,  Min Li

IPC分类号： H01L21/00

CPC分类号： H01L43/12

摘要： A method of forming a high performance MTJ in an MRAM array is disclosed. A Ta/Ru capping layer in a bottom conductor is sputter etched to remove the Ru layer and form an amorphous Ta capping layer. A key feature is a subsequent surface treatment of the Ta capping layer in a transient vacuum chamber where a self-annealing occurs and a surfactant layer is formed on the Ta surface. The resulting smooth and flat Ta surface promotes a smooth and flat surface in the MTJ layers which are subsequently formed on the surfactant layer. For a 0.3×0.6 micron MTJ bit size, a 35 to 40 Angstrom thick NiFe(18%) free layer, an AlOx barrier layer generated from a ROX oxidation of an 9 to 10 Angstrom thick Al layer, and a Ru/Ta/Ru capping layer are employed to give a dR/R of >40% and an RA of about 4000 ohm-μm2.

摘要翻译： 公开了一种在MRAM阵列中形成高性能MTJ的方法。 溅射蚀刻底部导体中的Ta / Ru覆盖层以去除Ru层并形成无定形Ta覆盖层。 一个关键的特征是在瞬态真空室中Ta覆盖层的后续表面处理，其中发生自退火并且在Ta表面上形成表面活性剂层。 所得到的平滑且平坦的Ta表面促进在表面活性剂层上随后形成的MTJ层中的光滑和平坦的表面。 对于0.3×0.6微米的MTJ位尺寸，35至40埃厚的NiFe（18％）自由层，由9至10埃厚的Al层的ROX氧化产生的AlO x势垒层，以及Ru / Ta / 使用Ru覆盖层来产生大于40％的dR / R和约4000欧姆 - 姆2的RA。

公开(公告)号：US20070015294A1

公开(公告)日：2007-01-18

申请号：US11522663

申请日：2006-09-18

申请人： Cheng Horng ,  Mao-Min Chen ,  Liubo Hong ,  Ru-Ying Tong

发明人： Cheng Horng ,  Mao-Min Chen ,  Liubo Hong ,  Ru-Ying Tong

IPC分类号： H01L21/00

CPC分类号： H01L43/12 ,  H01L43/08 ,  Y10S977/934 ,  Y10S977/935

摘要： An MTJ (magnetic tunneling junction) MRAM (magnetic random access memory) cell is formed on a conducting lead and magnetic keeper layer that is capped by a sputter-etched Ta layer. The Ta capping layer has a smooth surface as a result of the sputter-etching and that smooth surface promotes the subsequent formation of a lower electrode (pinning/pinned layer) with smooth, flat layers and a radical oxidized (ROX) Al tunneling barrier layer which is ultra-thin, smooth, and to has a high breakdown voltage. A seed layer of NiCr is formed on the sputter-etched capping layer of Ta. The resulting device has generally improved performance characteristics in terms of its switching characteristics, GMR ratio and junction resistance.

摘要翻译： 在由溅射蚀刻的Ta层覆盖的导电引线和磁保持层上形成MTJ（磁性隧道结）MRAM（磁性随机存取存储器）单元。 作为溅射蚀刻的结果，Ta覆盖层具有光滑的表面，并且光滑表面促进随后形成具有光滑的平坦层和自由基氧化（ROX）Al隧穿势垒层的下电极（钉扎/钉扎层） 其超薄，光滑，并具有高击穿电压。 在Ta的溅射蚀刻的覆盖层上形成NiCr种子层。 在其开关特性，GMR比和结电阻方面，所得到的器件通常具有改进的性能特性。