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179 条记录 (耗时 0.052 秒)

    Static random access memory with symmetric leakage-compensated bit line
    71.
    发明授权
    Static random access memory with symmetric leakage-compensated bit line 失效
    具有对称泄漏补偿位线的静态随机存取存储器

    公开(公告)号：US06707708B1

    公开(公告)日：2004-03-16

    申请号：US10241791

    申请日：2002-09-10

    申请人： Atila Alvandpour ,  Dinesh Somasekhar ,  Steven K. Hsu ,  Ram K. Krishnamurthy ,  Vivek K. De

    发明人： Atila Alvandpour ,  Dinesh Somasekhar ,  Steven K. Hsu ,  Ram K. Krishnamurthy ,  Vivek K. De

    IPC分类号： G11C1100

    CPC分类号： G11C11/412 ,  G11C11/419

    摘要： An eight-cell for static random access memory, the memory cell comprising cross-coupled inverters to store the information bit, two access nMOSFETs connected to local bit lines to access the stored information bit, and two nMOSFETs each having a gate connected to ground and coupled to the local bit lines and the cross-coupled inverters so that sub-threshold leakage currents to and from the local bit lines for a memory cell not being read are balanced.

    摘要翻译： 用于静态随机存取存储器的八单元，存储单元包括用于存储信息位的交叉耦合反相器，连接到局部位线的两个存取nMOSFET以访问所存储的信息位，以及两个nMOSFET，每个具有连接到地的栅极和 耦合到本地位线和交叉耦合的反相器，使得到达和从本地位线到不被读取的存储器单元的子阈值泄漏电流被平衡。

    Noise suppression for open bit line DRAM architectures
    72.
    发明授权
    Noise suppression for open bit line DRAM architectures 有权
    开放位线DRAM架构的噪声抑制

    公开(公告)号：US06496402B1

    公开(公告)日：2002-12-17

    申请号：US09690513

    申请日：2000-10-17

    申请人： Dinesh Somasekhar ,  Shih-Lien L. Lu ,  Vivek K. De

    发明人： Dinesh Somasekhar ,  Shih-Lien L. Lu ,  Vivek K. De

    IPC分类号： G11C506

    CPC分类号： G11C11/4097 ,  G11C7/02 ,  G11C11/4094

    摘要： An open bit line dynamic random access memory (DRAM) architecture uses a multiple layer bit line configuration to reduce coupling between switching bit lines in the device. In one approach, each successive cell within a row of DRAM cells is coupled to a bit line segment that is on a different metallization layer than a previous cell in the row. Shielding members are also provided between adjacent bit lines on a common metallization layer to further reduce noise coupling. Functionality is also provided for reducing the effect of word line to bit line coupling in the DRAM device using dummy signal injection techniques. In this manner, common mode noise that could otherwise saturate one or more sense amplifiers within the DRAM device is reduced or eliminated before such saturation can take place. In one approach, dummy cells and reference cells are provided for use in performing the signal injection. The principles of the present invention are particularly well suited for use within embedded DRAM structures where low charge storage capacity within individual cells reduces the signal voltage levels that are achievable.

    摘要翻译： 开放式位线动态随机存取存储器（DRAM）架构使用多层位线配置来减少器件中的开关位线之间的耦合。 在一种方法中，DRAM单元行内的每个连续单元被耦合到位于与行中的先前单元格不同的金属化层上的位线段。 屏蔽构件也设置在公共金属化层上的相邻位线之间，以进一步减少噪声耦合。 还提供了功能，用于使用虚拟信号注入技术来减少DRAM设备中字线对位线耦合的影响。 以这种方式，在这种饱和可能发生之前，可以减少或消除在DRAM装置内可以饱和一个或多个感测放大器的共模噪声。 在一种方法中，提供虚拟单元和参考单元用于执行信号注入。 本发明的原理特别适合于在嵌入式DRAM结构中使用，其中各个单元内的低电荷存储容量降低可实现的信号电压电平。

    Low-leakage MOS planar capacitors for use within DRAM storage cells
    73.
    发明授权
    Low-leakage MOS planar capacitors for use within DRAM storage cells 有权
    用于DRAM存储单元的低泄漏MOS平面电容器

    公开(公告)号：US06421269B1

    公开(公告)日：2002-07-16

    申请号：US09690687

    申请日：2000-10-17

    申请人： Dinesh Somasekhar ,  Shih-Lien L. Lu ,  Vivek K. De

    发明人： Dinesh Somasekhar ,  Shih-Lien L. Lu ,  Vivek K. De

    IPC分类号： G11C1124

    CPC分类号： H01L29/66181 ,  H01L27/0218 ,  H01L27/10805 ,  H01L29/94

    摘要： A planar capacitor for use within a dynamic random access memory (DRAM) cell is operated within semiconductor depletion during normal storage operations to increase the charge retention time of the capacitor. Operation within semiconductor depletion allows a significant increase in charge retention time in a capacitor for which gate oxide leakage is the predominant leakage mechanism. The voltages that are applied to the storage cell during DRAM operation are controlled so that the storage capacitor within the cell remains in depletion during storage of both a logic zero and a logic one. Although the capacitance of the cell is decreased by operating in depletion, the charge retention time of the cell can be increased by multiple orders of magnitude. In one application, the inventive structures and techniques are implemented within a DRAM device that is embedded within logic circuitry.

    摘要翻译： 用于动态随机存取存储器（DRAM）单元的平面电容器在正常存储操作期间在半导体耗尽中运行，以增加电容器的电荷保留时间。 在半导体耗尽中的操作允许在电容器中的电荷保持时间显着增加，其中栅极氧化物泄漏是主要的泄漏机制。 控制在DRAM操作期间施加到存储单元的电压，使得在存储逻辑0和逻辑1期间，单元内的存储电容器保持耗尽。 尽管电池的电容通过在耗尽中操作而降低，但电池的电荷保持时间可以增加多个数量级。 在一个应用中，本发明的结构和技术在嵌入在逻辑电​​路内的DRAM器件内实现。

    Circuit including forward body bias from supply voltage and ground nodes
    74.
    发明授权
    Circuit including forward body bias from supply voltage and ground nodes 有权
    电路包括电源电压和接地节点的正向偏置

    公开(公告)号：US06593799B2

    公开(公告)日：2003-07-15

    申请号：US09957996

    申请日：2001-09-21

    申请人： Vivek K. De ,  Ali Keshavarzi ,  Siva G. Narendra ,  Shekhar Y. Borkar

    发明人： Vivek K. De ,  Ali Keshavarzi ,  Siva G. Narendra ,  Shekhar Y. Borkar

    IPC分类号： H03K301

    CPC分类号： H01L27/0928 ,  H01L29/1087 ,  H03K19/0948

    摘要： One embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. Another embodiment of the invention includes a semiconductor circuit including a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors. Still another embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. The circuit also includes a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors.

    摘要翻译： 本发明的一个实施例包括一个包括接地电压节点以提供接地电压的半导体电路，以及具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。 本发明的另一个实施例包括一个半导体电路，其包括提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型体的nFET晶体管，以使nFET晶体管的本体偏置转向。 本发明的另一个实施例包括一个包括接地电压节点以提供接地电压的半导体电路，以及具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。 该电路还包括用于提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型主体的nFET晶体管，以使nFET晶体管的主体偏置转向。

    Selective cooling of an integrated circuit for minimizing power loss
    77.
    发明授权
    Selective cooling of an integrated circuit for minimizing power loss 有权
    集成电路的选择性冷却，以最大限度地减少功率损耗

    公开(公告)号：US06825687B2

    公开(公告)日：2004-11-30

    申请号：US10230466

    申请日：2002-08-29

    申请人： Ali Keshavarzi ,  Jaume A. Segura ,  Siva G. Narendra ,  Vivek K. De

    发明人： Ali Keshavarzi ,  Jaume A. Segura ,  Siva G. Narendra ,  Vivek K. De

    IPC分类号： H03K1716

    CPC分类号： H03K19/0016 ,  H01L27/0251

    摘要： An apparatus and method for reducing leakage current of transistors used in an integrated circuit, which selectively switch a processor circuit in the integrated circuit to a standby state. A cooling device is included and selectively located in an area of the integrated circuit that is in close proximity to a transistor used to switch a processor circuit between active and standby states. The cooling device cools the transistor in order to improve both its leakage and active current states, thereby increasing efficiency of the transistor and reducing its leakage current.

    摘要翻译： 一种用于降低在集成电路中使用的晶体管的泄漏电流的装置和方法，其选择性地将集成电路中的处理器电路切换到待机状态。 包括冷却装置并且选择性地位于集成电路的紧邻用于在主动状态和待机状态之间切换处理器电路的晶体管的区域中。 冷却装置冷却晶体管，以改善其泄漏和有功电流状态，从而提高晶体管的效率并减少其漏电流。

    Transistors providing desired threshold voltage and reduced short channel effects with forward body bias
    78.
    发明授权
    Transistors providing desired threshold voltage and reduced short channel effects with forward body bias 失效
    晶体管提供期望的阈值电压和减少的短通道效应与前向偏置

    公开(公告)号：US06232827B1

    公开(公告)日：2001-05-15

    申请号：US09078388

    申请日：1998-05-13

    申请人： Vivek K. De ,  Ali Keshavarzi ,  Siva G. Narendra ,  Shekhar Y. Borkar

    发明人： Vivek K. De ,  Ali Keshavarzi ,  Siva G. Narendra ,  Shekhar Y. Borkar

    IPC分类号： G05F110

    CPC分类号： H01L27/0928 ,  H01L29/1087 ,  H03K19/0948

    摘要： In one embodiment, a semiconductor circuit includes a first group of field effect transistors having a body and parameters including a net channel doping level DL1. The circuit also includes a conductor to provide a first voltage to the body to forward body bias the first group of transistors, the first group of transistors having a forward body bias threshold voltage (VtFBB) when forward body biased, wherein DL1 is at least 25% higher than a net channel doping level in the first group of transistors that would result in a zero body bias threshold voltage equal to VtFBB, with the parameters other than the net channel doping level being unchanged. In another embodiment, the semiconductor circuit includes a first circuit including a first group of field effect transistors having a body. The circuit also includes a first voltage source to provide a first voltage to the body such that the field effect transistors have a forward body bias, the first voltage being at a level leading to the circuit experiencing a reduced rate of soft error failures as compared to when the circuit is not forward biased.

    摘要翻译： 在一个实施例中，半导体电路包括具有主体的第一组场效应晶体管和包括净通道掺杂水平DL1的参数。 该电路还包括导体，用于向主体提供第一电压以使第一组晶体管偏置，第一组晶体管在正向偏置时具有正向偏置阈值电压（VtFBB），其中DL1至少为25 高于第一组晶体管中的净通道掺杂水平，其将导致零体偏置阈值电压等于VtFBB，其中除了净通道掺杂水平之外的参数不变。 在另一实施例中，半导体电路包括第一电路，其包括具有主体的第一组场效应晶体管。 电路还包括第一电压源，以向主体提供第一电压，使得场效应晶体管具有正向体偏置，第一电压处于导致电路经历软错误故障率降低的水平，与 当电路没有正向偏置时。

    Insulated channel field effect transistor with an electric field terminal region
    79.
    发明授权
    Insulated channel field effect transistor with an electric field terminal region 有权

    公开(公告)号：US06734498B2

    公开(公告)日：2004-05-11

    申请号：US09165483

    申请日：1998-10-02

    申请人： Ali Keshavarzi ,  Vivek K. De ,  Siva G. Narendra

    发明人： Ali Keshavarzi ,  Vivek K. De ,  Siva G. Narendra

    IPC分类号： H01L2701

    CPC分类号： H01L29/78603 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78606 ,  H01L29/78645 ,  H01L29/78648

    摘要： In one embodiment, the invention includes a field effect transistor having a substrate, a source, and a drain. An electric field terminal region is lower than the source and drain and is in the substrate. A body is above the electric field terminal region between the source and drain. In another embodiment, the invention includes a field effect transistor having an insulator layer and a body above the insulator layer between a source and a drain. A substrate is below the insulator layer. A gate is above the body and between the source and drain. An electric field terminal region is included in the substrate. The body may be undoped and the threshold voltage be set by setting the distance between the insulator layer and a gate insulator. The body, substrate, and electric field terminal region may float or one or more of them may be biased.

    Silicon on insulator device design having improved floating body effect
    80.
    发明授权
    Silicon on insulator device design having improved floating body effect 失效
    硅绝缘体器件设计具有改善的浮体效应

    公开(公告)号：US06632686B1

    公开(公告)日：2003-10-14

    申请号：US09672696

    申请日：2000-09-29

    申请人： Ali Keshavarzi ,  Siva G. Narendra ,  James W. Tschanz ,  Vivek K. De

    发明人： Ali Keshavarzi ,  Siva G. Narendra ,  James W. Tschanz ,  Vivek K. De

    IPC分类号： H01L2166

    CPC分类号： G06F17/5068 ,  G06F17/5063 ,  H01L27/1203

    摘要： A method is provided for designing an electronic device. This may include determining a capacitance ratio of a design of the electronic device and altering the design so as to increase the capacitance ratio of said electronic device. The capacitance ratio may be Cdj/(Cdj+Csj+CBOX), where Cdj is a capacitance of a drain-body junction, Csj is a capacitance of a source-body junction and CBOX is a capacitance of a buried oxide layer.

    摘要翻译： 提供了一种用于设计电子设备的方法。 这可以包括确定电子设备的设计的电容比并改变设计以增加所述电子设备的电容比。 电容比可以是C dj /（C dj + C sj + C BOX ），其中C dj 是漏 - 体结的电容C sj 是源体结的电容，C BOX 是掩埋氧化物层的电容。