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1.发明授权Transistors providing desired threshold voltage and reduced short channel effects with forward body bias 失效晶体管提供期望的阈值电压和减少的短通道效应与前向偏置公开(公告)号：US06232827B1
公开(公告)日：2001-05-15
申请号：US09078388
申请日：1998-05-13
IPC分类号： G05F110
CPC分类号： H01L27/0928 , H01L29/1087 , H03K19/0948
摘要： In one embodiment, a semiconductor circuit includes a first group of field effect transistors having a body and parameters including a net channel doping level DL1. The circuit also includes a conductor to provide a first voltage to the body to forward body bias the first group of transistors, the first group of transistors having a forward body bias threshold voltage (VtFBB) when forward body biased, wherein DL1 is at least 25% higher than a net channel doping level in the first group of transistors that would result in a zero body bias threshold voltage equal to VtFBB, with the parameters other than the net channel doping level being unchanged. In another embodiment, the semiconductor circuit includes a first circuit including a first group of field effect transistors having a body. The circuit also includes a first voltage source to provide a first voltage to the body such that the field effect transistors have a forward body bias, the first voltage being at a level leading to the circuit experiencing a reduced rate of soft error failures as compared to when the circuit is not forward biased.
摘要翻译： 在一个实施例中，半导体电路包括具有主体的第一组场效应晶体管和包括净通道掺杂水平DL1的参数。 该电路还包括导体，用于向主体提供第一电压以使第一组晶体管偏置，第一组晶体管在正向偏置时具有正向偏置阈值电压（VtFBB），其中DL1至少为25 高于第一组晶体管中的净通道掺杂水平，其将导致零体偏置阈值电压等于VtFBB，其中除了净通道掺杂水平之外的参数不变。 在另一实施例中，半导体电路包括第一电路，其包括具有主体的第一组场效应晶体管。 电路还包括第一电压源，以向主体提供第一电压，使得场效应晶体管具有正向体偏置，第一电压处于导致电路经历软错误故障率降低的水平，与 当电路没有正向偏置时。
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公开(公告)号：US06218895B1
公开(公告)日：2001-04-17
申请号：US09078424
申请日：1998-05-13
IPC分类号： H01L2976
CPC分类号： H01L27/0928 , H01L29/1087 , H03K19/0948
摘要： In one embodiment to the invention, a semiconductor circuit includes a substrate and a first well formed in the substrate. A first group of field effect transistors is formed in the first well and has a first body. The circuit includes a first body voltage to the first body to forward body bias the first group of field effect transistors. The circuit includes a first isolation structure to contain the first body voltage in the first well. In another embodiment, the circuit further includes a second group of field effect transistors having a non-forward body bias and the first isolation structure prevents the first body voltage from influencing a voltage of a body of the second group of field effect transistors. In yet another embodiment, a second isolation structure adjacent to the second well contain a second body voltage in a second well holding the second group of field effect transistors.
摘要翻译： 在本发明的一个实施例中，半导体电路包括衬底和形成在衬底中的第一阱。 在第一阱中形成第一组场效应晶体管，并且具有第一主体。 该电路包括第一体电压，以使第一组场效应晶体管偏转第一体。 电路包括第一隔离结构，以在第一阱中容纳第一体电压。 在另一实施例中，电路还包括具有非正向主体偏置的第二组场效应晶体管，并且第一隔离结构防止第一体电压影响第二组场效应晶体管的主体的电压。 在另一个实施例中，与第二阱相邻的第二隔离结构在保持第二组场效应晶体管的第二阱中包含第二体电压。
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公开(公告)号：US06411156B1
公开(公告)日：2002-06-25
申请号：US09224575
申请日：1998-12-30
IPC分类号： H03K301
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , H01L27/0928 , H01L29/1087 , H03K19/00384 , H03K19/0948 , H03K2217/0018 , Y02D10/126 , Y02D10/172
摘要： In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control a setting of a body bias signal to control body biases provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal being responsive to an input signal to the control circuitry. In some embodiments, the invention involves a system including an integrated circuit. The system a circuit including transistors. The system further includes control circuitry to control settings of a body bias signal, a supply voltage signal, and a clock signal to control body biases, supply voltages, and clock frequencies provided in the circuit to at least partially control a parameter of the integrated circuit, the setting of the body bias signal, supply voltage signal, and clock signal being responsive to an input signal to the control circuitry.
摘要翻译： 在一些实施例中，本发明涉及包括集成电路的系统。 该系统包括晶体管的电路。 该系统还包括控制电路，用于控制体偏置信号的设置以控制设置在电路中的身体偏压，以至少部分地控制集成电路的参数，体偏置信号的设置响应于输入信号 控制电路。 在一些实施例中，本发明涉及包括集成电路的系统。 该系统包括晶体管的电路。 该系统还包括控制电路，用于控制体偏置信号，电源电压信号和时钟信号的设置，以控制电路中提供的体偏置，电源电压和时钟频率，以至少部分地控制集成电路的参数 ，所述体偏置信号，电源电压信号和时钟信号的设置响应于控制电路的输入信号。
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4.发明授权公开(公告)号：US06300819B1
公开(公告)日：2001-10-09
申请号：US09078395
申请日：1998-05-13
IPC分类号： G05F110
CPC分类号： H01L27/0928 , H01L29/1087 , H03K19/0948
摘要： One embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. Another embodiment of the invention includes a semiconductor circuit including a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors. Still another embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. The circuit also includes a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors.
摘要翻译： 本发明的一个实施例包括一个半导体电路，该半导体电路包括提供接地电压的接地电压节点和具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。 本发明的另一个实施例包括一个半导体电路，其包括提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型体的nFET晶体管，以使nFET晶体管的本体偏置转向。 本发明的另一个实施例包括一个包括接地电压节点以提供接地电压的半导体电路，以及具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。 该电路还包括用于提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型主体的nFET晶体管，以使nFET晶体管的主体偏置转向。
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5.发明授权
公开(公告)号：US06100751A
公开(公告)日：2000-08-08
申请号：US078432
申请日：1998-05-13
IPC分类号： H01L27/092 , H01L29/10 , H03K19/0948 , H03L7/081 , H03L7/099 , G05F1/10
CPC分类号： H03L7/0812 , H01L27/0928 , H01L29/1087 , H03K19/0948 , H03L7/0995
摘要： In one embodiment of the invention, a semiconductor circuit includes a first group of field effect transistors that are forward body biased and have threshold voltages and a second group of field effect transistors that are not forward body biased and have threshold voltages that are higher than the threshold voltages of the first group of field transistors. In another embodiment of the invention, a semiconductor circuit includes first and second groups of field effect transistors. The circuit includes voltage source circuitry to provide voltage signals to bodies of the first group of field effect transistors to forward body bias the transistors of the first group. When the voltage signals are applied, the transistors of the first group have lower threshold voltages than do the transistors of the second group, except that there may be unintentional variations in threshold voltages due to parameter variations. Other aspects of the invention include forward biased decoupling transistors and a method of testing for leakage.
摘要翻译： 在本发明的一个实施例中，半导体电路包括正向偏置并具有阈值电压的第一组场效应晶体管和不是正向主体偏置的第二组场效应晶体管，并且具有高于 第一组场效应晶体管的阈值电压。 在本发明的另一个实施例中，半导体电路包括第一和第二组场效应晶体管。 电路包括电压源电路，用于向第一组场效应晶体管的主体提供电压信号，以将第一组的晶体管的体偏置转发。 当施加电压信号时，除了由于参数变化引起的阈值电压可能存在无意的变化之外，第一组的晶体管具有比第二组的晶体管低的阈值电压。 本发明的其它方面包括正向偏置去耦晶体管和一种测试泄漏的方法。
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6.发明授权公开(公告)号：US06484265B2
公开(公告)日：2002-11-19
申请号：US09224573
申请日：1998-12-30
IPC分类号： G06F132
CPC分类号： G06F1/324 , G06F1/26 , G06F1/32 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： In some embodiments, the invention includes a system having a processor and control circuitry. The control circuitry controls a setting of a body bias signal to control body biases provided in the processor to at least partially control a parameter of the processor, wherein the control circuitry controls the setting responsive to processor signal resulting for execution of software. The control circuitry may further control settings of a supply voltage signal and a clock signal to control the parameter. More than one parameter may be controlled. Examples of the parameters include performance, power consumption, and temperature.
摘要翻译： 在一些实施例中，本发明包括具有处理器和控制电路的系统。 控制电路控制身体偏置信号的设置以控制处理器中提供的身体偏压，以至少部分地控制处理器的参数，其中控制电路根据处理器信号控制结果，从而执行软件。 控制电路还可以控制电源电压信号和时钟信号的设置以控制参数。 可以控制多个参数。 参数的示例包括性能，功耗和温度。
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公开(公告)号：US06272666B1
公开(公告)日：2001-08-07
申请号：US09224574
申请日：1998-12-30
IPC分类号： G06F1750
CPC分类号： G01R31/2882 , G01R31/3016
摘要： In some embodiments, the invention includes a system having first and second domains. The system includes a first performance detection circuitry including some transistors of the first domain to provide a first performance rating signal indicative of transistor switching rates of the first domain. The system includes second performance detection circuitry including some transistors of the second domain to provide a second performance rating signal indicative of transistor switching rates the second domain. The system further includes control circuitry to receive the first and second performance rating signals and control a setting for a body bias signal for the first domain and control a setting for a body bias signal for the second domain responsive to the performance rating signals. In some embodiments, the control circuitry also provides supply voltage signals and clock signals responsive to the performance signals. The first and second domains may have clock signals with the same frequency and the bias values are set such that the transistors of the first and second domains can switch properly while the first and second domains have the clock signals and wherein one of the first and second domains operates at less than optimal performance.
摘要翻译： 在一些实施例中，本发明包括具有第一和第二域的系统。 该系统包括第一性能检测电路，其包括第一域的一些晶体管，以提供指示第一域的晶体管切换速率的第一性能评估信号。 该系统包括第二性能检测电路，其包括第二域的一些晶体管，以提供指示第二域的晶体管切换速率的第二性能评估信号。 该系统还包括控制电路，用于接收第一和第二性能评定信号并且控制针对第一域的体偏置信号的设置，并且响应于性能等级信号来控制针对第二域的体偏置信号的设置。 在一些实施例中，控制电路还响应于性能信号提供电源电压信号和时钟信号。 第一和第二域可以具有相同频率的时钟信号，并且偏置值被设置为使得第一和第二域的晶体管可以正确地切换，而第一和第二域具有时钟信号，并且其中第一和第二域中的一个 域以不到最佳性能运行。
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8.发明授权公开(公告)号：US06593799B2
公开(公告)日：2003-07-15
申请号：US09957996
申请日：2001-09-21
IPC分类号： H03K301
CPC分类号： H01L27/0928 , H01L29/1087 , H03K19/0948
摘要： One embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. Another embodiment of the invention includes a semiconductor circuit including a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors. Still another embodiment of the invention includes a semiconductor circuit including a ground voltage node to provide a ground voltage and pFET transistors having an n-type body electrically coupled to the ground voltage node to forward body bias the pFET transistors. The circuit also includes a supply voltage node to provide a supply voltage and nFET transistors having a p-type body electrically coupled to the supply voltage node to forward body bias the nFET transistors.
摘要翻译： 本发明的一个实施例包括一个包括接地电压节点以提供接地电压的半导体电路，以及具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。 本发明的另一个实施例包括一个半导体电路，其包括提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型体的nFET晶体管，以使nFET晶体管的本体偏置转向。 本发明的另一个实施例包括一个包括接地电压节点以提供接地电压的半导体电路，以及具有电耦合到接地电压节点的n型体的pFET晶体管，以使pFET晶体管的偏置正向。 该电路还包括用于提供电源电压的电源电压节点和具有电耦合到电源电压节点的p型主体的nFET晶体管，以使nFET晶体管的主体偏置转向。
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公开(公告)号：US20100219516A1
公开(公告)日：2010-09-02
申请号：US12660305
申请日：2010-02-24
申请人： Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
发明人： Siva G. Narendra , James W. Tschanz , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
IPC分类号： H01L23/495
CPC分类号： H01L25/0657 , H01L25/18 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2225/06513 , H01L2225/06527 , H01L2924/00014 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译： 公开了一种集成电路（IC）封装。 IC封装包括第一裸片; 以及以三维封装布局结合到CPU管芯的第二管芯。
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公开(公告)号：US20100115301A1
公开(公告)日：2010-05-06
申请号：US12684257
申请日：2010-01-08
申请人： Siva G. Narendra , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
发明人： Siva G. Narendra , Howard A. Wilson , Donald S. Gardner , Peter Hazucha , Gerhard Schrom , Tanay Karnik , Nitin Borkar , Vivek K. De , Shekhar Y. Borkar
IPC分类号： G06F1/26
CPC分类号： H01L25/18 , G06F1/189 , G06F1/26 , H01L25/0657 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2924/00011 , H01L2924/00014 , H01L2924/3011 , H01L2224/0401
摘要： A central processing unit (CPU) is disclosed. The CPU includes a CPU die; and a voltage regulator die bonded to the CPU die in a three dimensional packaging layout.
摘要翻译： 公开了一种中央处理单元（CPU）。 CPU包括CPU管芯; 以及以三维封装布局结合到CPU裸片的电压调节器芯片。
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