Data block cluster processing in a wireless device
    71.
    发明申请
    Data block cluster processing in a wireless device 审中-公开
    无线设备中的数据块集群处理

    公开(公告)号:US20080267100A1

    公开(公告)日:2008-10-30

    申请号:US11796167

    申请日:2007-04-27

    IPC分类号: H04B7/00 H04B1/38 H04B1/66

    CPC分类号: H04B1/707 H04L69/18 H04W88/02

    摘要: A wireless device includes a case, user interface, an antenna, first processing resources, and second processing resources. The first processing resources couple to the antenna and to the second processing resources and receive and operate upon a data signal transmitted by a transmitting wireless device. In its processing operations, the first processing resources produces decoded data blocks and writes the decoded data blocks to a data buffer. When a processing resource threshold is met with regard to the plurality of decoded data blocks, the first processing resources issue a service processing interrupt to the second processing resources. In response to the service processing interrupt, the second processing resources retrieve the plurality of decoded data blocks from the data buffer in response to the service processing interrupt and process the plurality of decoded data blocks.

    摘要翻译: 无线装置包括壳体,用户接口,天线,第一处理资源和第二处理资源。 第一处理资源耦合到天线和第二处理资源,并且接收和操作由发送无线设备发送的数据信号。 在其处理操作中,第一处理资源产生解码数据块,并将解码的数据块写入数据缓冲器。 当满足多个解码数据块的处理资源阈值时,第一处理资源向第二处理资源发出业务处理中断。 响应于服务处理中断,第二处理资源响应于服务处理中断从数据缓冲器检索多个解码的数据块,并处理多个解码的数据块。

    SINGLE CHIP WIRELESS TRANSCEIVER OPERABLE TO PERFORM VOICE, DATA AND RADIO FREQUENCY (RF) PROCESSING
    72.
    发明申请
    SINGLE CHIP WIRELESS TRANSCEIVER OPERABLE TO PERFORM VOICE, DATA AND RADIO FREQUENCY (RF) PROCESSING 有权
    单芯片无线收发器可操作语音,数据和无线电频率(RF)处理

    公开(公告)号:US20080153541A1

    公开(公告)日:2008-06-26

    申请号:US11959146

    申请日:2007-12-18

    IPC分类号: H04M1/00

    CPC分类号: H04B1/40

    摘要: A single chip wireless transceiver operable to perform voice, data and radio frequency (RF) processing is provided. This processing may be divided between various processing modules. This single chip includes a processing module having an ARM microprocessor and a digital signal processor (DSP), an RF section, and an interface module. The processing module converts an outbound voice signal into an outbound voice symbol stream, converts an inbound voice symbol stream into an inbound voice signal, converts outbound data into an outbound data symbol stream, and converts an inbound data symbol stream into inbound data. These functions may be divided between the ARM microprocessor and DSP, where the DSP supports physically layer type applications and the ARM microprocessor supports higher layer applications. Further bifurcation may be based on voice applications, data applications, and/or RF control. The RF section converts an inbound RF voice signal into the inbound voice symbol stream, converts the outbound voice symbol stream into an outbound RF voice signal, converts an inbound RF data signal into the inbound data symbol stream, and converts the outbound data symbol stream into an outbound RF data signal. The interface module provides coupling between the processing module, the RF section, and with off-chip circuits.

    摘要翻译: 提供可操作以执行语音,数据和射频(RF)处理的单芯片无线收发器。 该处理可以在各种处理模块之间划分。 该单芯片包括具有ARM微处理器和数字信号处理器(DSP),RF部分和接口模块的处理模块。 处理模块将出站语音信号转换为出站语音符号流,将入站语音符号流转换为入站语音信号,将出站数据转换为出站数据符号流,并将入站数据符号流转换为入站数据。 这些功能可以分为ARM微处理器和DSP,DSP支持物理层类型应用,ARM微处理器支持更高层应用。 进一步的分叉可以基于语音应用,数据应用和/或RF控制。 RF部分将进入的RF语音信号转换成入站语音符号流,将出站的语音符号流转换成出站的RF语音信号,将入站的RF数据信号转换成入站数据符号流,并将出站的数据符号流转换成 出站RF数据信号。 接口模块提供处理模块,RF部分和片外电路之间的耦合。

    Frequency domain equalizer for dual antenna radio
    74.
    发明申请
    Frequency domain equalizer for dual antenna radio 有权
    双天线收音机的频域均衡器

    公开(公告)号:US20080075209A1

    公开(公告)日:2008-03-27

    申请号:US11524584

    申请日:2006-09-21

    IPC分类号: H04L1/02 H04B1/10

    摘要: A Radio Frequency (RF) receiver includes a RF front end and a baseband processing module coupled to the RF front end that is operable to receive a time domain signal that includes time domain training symbols and time domain data symbols. The baseband processing module includes a channel estimator operable to process the time domain training symbols to produce a time domain channel estimate, a Fast Fourier Transformer operable to convert the time domain channel estimate to the frequency domain to produce a frequency domain channel estimate, a weight calculator operable to produce frequency domain equalizer coefficients based upon the frequency domain channel estimate, an Inverse Fast Fourier Transformer operable to converting the frequency domain equalizer coefficients to the time domain to produce time domain equalizer coefficients, and an equalizer operable to equalize the time domain data symbols using the time domain equalizer coefficients.

    摘要翻译: 射频(RF)接收机包括RF前端和耦合到RF前端的基带处理模块,其可操作以接收包括时域训练符号和时域数据符号的时域信号。 基带处理模块包括信道估计器,其可操作以处理时域训练符号以产生时域信道估计;快速傅立叶变换器,其可操作以将时域信道估计转换为频域以产生频域信道估计,权重 计算器,其可操作以基于频域信道估计产生频域均衡器系数;反傅里叶变换器,其可操作以将频域均衡器系数转换到时域以产生时域均衡器系数;以及均衡器,其可操作以均衡时域数据 符号使用时域均衡器系数。

    Frequency domain equalizer for single antenna radio
    75.
    发明申请
    Frequency domain equalizer for single antenna radio 失效
    用于单天线无线电的频域均衡器

    公开(公告)号:US20080075180A1

    公开(公告)日:2008-03-27

    申请号:US11641933

    申请日:2006-12-19

    IPC分类号: H04K1/10 H04B1/10

    摘要: A Radio Frequency (RF) transceiver includes a RF front end and a baseband processing module coupled to the RF front end that is operable to receive a time domain signal that includes time domain training symbols and time domain data symbols. The baseband processing module processes the time domain training symbols to produce a time domain channel estimate, Fast Fourier Transformer operations that convert the time domain channel estimate to the frequency domain to produce a frequency domain channel estimate, weight calculation operations that produce frequency domain equalizer coefficients based upon the frequency domain channel estimate, Inverse Fast Fourier Transformer operations that convert the frequency domain equalizer coefficients to the time domain to produce time domain equalizer coefficients, and equalization operations that equalize the time domain data symbols using the time domain equalizer coefficients.

    摘要翻译: 射频(RF)收发器包括RF前端和耦合到RF前端的基带处理模块,其可操作以接收包括时域训练符号和时域数据符号的时域信号。 基带处理模块处理时域训练符号以产生时域信道估计,将时域信道估计转换为频域以产生频域信道估计的快速傅里叶变换器操作,产生频域均衡器系数的权重计算操作 基于频域信道估计,将频域均衡器系数转换到时域以产生时域均衡器系数的快速傅里叶逆变换器操作,以及使用时域均衡器系数均衡时域数据符号的均衡操作。

    Radio frequency integrated circuit having frequency dependent noise mitigation with spectrum spreading
    76.
    发明申请
    Radio frequency integrated circuit having frequency dependent noise mitigation with spectrum spreading 有权
    射频集成电路具有频谱扩展的频率相关噪声抑制

    公开(公告)号:US20080024339A1

    公开(公告)日:2008-01-31

    申请号:US11641562

    申请日:2006-12-18

    IPC分类号: H03M1/00

    CPC分类号: H04B15/06

    摘要: A radio frequency integrated circuit (RFIC) includes a low noise amplifier that amplifies an inbound radio frequency (RF) signal to produce an amplified RF signal. A down conversion module converts the amplified RF signal to a down converted signal based on a local oscillation. An analog to digital conversion (ADC) module coupled to convert the down converted signal into a digital signal. A baseband processing module converts the digital signal into inbound data, wherein at least one function of the baseband processing module is clocked by a plurality of baseband clock signals A clock module produces the plurality of baseband clock signals, wherein the clock module detects an interference condition when frequency dependent noise components associated with at least one of the plurality of baseband clock signals are inside a frequency band associated with the inbound RF signal, and spreads the spectrum of the at least one of the plurality of baseband clock signals when the interference condition is detected.

    摘要翻译: 射频集成电路(RFIC)包括放大入射射频(RF)信号以产生放大的RF信号的低噪声放大器。 降频转换模块基于本地振荡将放大的RF信号转换为下变频信号。 模数转换(ADC)模块耦合以将下变频信号转换为数字信号。 基带处理模块将数字信号转换为入站数据,其中基带处理模块的至少一个功能由多个基带时钟信号A计时。时钟模块产生多个基带时钟信号,其中时钟模块检测干扰条件 当与所述多个基带时钟信号中的至少一个相关联的频率相关噪声分量在与所述入站RF信号相关联的频带内时,并且当所述干扰条件是所述干扰条件是时,扩展所述多个基带时钟信号中的至少一个的频谱 检测到。

    Beacon detection system for sharing spectrum between wireless
communications systems and fixed microwave systems
    77.
    发明授权
    Beacon detection system for sharing spectrum between wireless communications systems and fixed microwave systems 失效
    信标检测系统,用于在无线通信系统和固定微波系统之间共享频谱

    公开(公告)号:US5361258A

    公开(公告)日:1994-11-01

    申请号:US142533

    申请日:1993-10-22

    摘要: A system for spectrum sharing between a point-to-point microwave system and a TDM/TDMA wireless communications system in a common geographical area is described. Each transmitter/receiver in the point-to-point microwave system transmits, in addition to its normal information signal, a beacon signal which is uniquely associated with the receiver receive frequency. In selecting uplink and downlink frequencies for port assignment, each port monitors the beacon frequencies and selects as uplink and downlink frequencies, frequencies which associated beacons fall below a predetermined threshold. Similarly, before accessing the wireless communications system through a selected port, a portable monitors the beacons associated with the selected port's uplink frequency. If the beacon associated with the uplink frequency exceeds a threshold, the portable selects an alternate port through which to access the network. Also, during a call an emergency link transfer to another port is made if the monitored beacon corresponding to the portable's uplink frequency rises above the threshold.

    摘要翻译: 描述了在公共地理区域中的点对点微波系统和TDM / TDMA无线通信系统之间的频谱共享系统。 点对点微波系统中的每个发射机/接收机除了正常的信息信号之外还发送与接收机接收频率唯一相关联的信标信号。 在选择用于端口分配的上行链路和下行链路频率时,每个端口监视信标频率并选择上行链路和下行链路频率,相关信标的频率低于预定阈值。 类似地,在通过所选择的端口访问无线通信系统之前,便携式监视与所选端口的上行链路频率相关联的信标。 如果与上行链路频率相关联的信标超过阈值,则便携式选择用于接入网络的备用端口。 此外,在呼叫期间,如果与便携式上行链路频率对应的被监视信标上升到阈值以上,则进行到另一端口的紧急链路传送。

    Technique for jointly performing bit synchronization and error detection
in a TDM/TDMA system
    78.
    发明授权
    Technique for jointly performing bit synchronization and error detection in a TDM/TDMA system 失效
    在TDM / TDMA系统中共同执行比特同步和错误检测的技术

    公开(公告)号:US5084891A

    公开(公告)日:1992-01-28

    申请号:US404946

    申请日:1989-09-08

    摘要: A technique for bit synchronization and error detection of received digital data bursts in a TDM/TDMA system, such as that which will be used with low power portable digital telephony. A cyclically redundant codeword, e.g. a (161,147) codeword, is formed for transmission, using e.g. either a TDM packet or TDMA burst. The first and last bits in the codeword are then inverted to form a first set of marker bits. At a receiver, a second set of marker bits is inserted into a received word, again through inverting the first and last bits. The resulting marked word is then rotated by a pre-determined number of bits to place potentially erroneous bits at the end of this word. A multi-bit timing syndrome value is then determined and is used to access a look-up table for a value of bit slippage. The received word is advanced or retarded as specified by the bit slippage value to yield an intermediate word. The marker bits are removed from the intermediate word to yield an unmarked word for which an error syndrome value is determined. If the error syndrome value is zero, then the unmarked word is a synchronized substantially error-free codeword. If the unmarked word contains excessive bit slippage or bit errors indicated by an excessive value of the timing syndrome or a non-zero valued error syndrome, an indication is provided to ignore this word.

    摘要翻译: 用于TDM / TDMA系统中接收的数字数据脉冲串的比特同步和错误检测的技术,例如将与低功率便携式数字电话一起使用的技术。 循环冗余码字,例如。 一个(161,147)码字被形成用于传输,使用例如 TDM分组或TDMA突发。 码字中的第一和最后一位然后被反转以形成第一组标记位。 在接收机处,通过反转第一位和最后位,再次将第二组标记位插入接收到的字中。 然后将得到的标记字旋转预定数量的位,以将潜在的错误位置于该字的末尾。 然后确定多位定时综合征值,并且用于访问查询表中的位打滑值。 接收到的字是由位滑移值指定的高级或延迟,以产生一个中间字。 标记位从中间字移除以产生确定错误校正值的未标记字。 如果错误校正值为零,则未标记的字是同步的基本上无错误的码字。 如果未标记的字包含由定时综合征的过大值或非零值错误综合征指示的过多的位滑动或位错误,则提供忽略该字的指示。