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71.发明申请Drive Circuit of Display Apparatus, Pulse Generation Method, Display Apparatus 有权显示装置的驱动电路，脉冲发生方法，显示装置公开(公告)号：US20090115758A1
公开(公告)日：2009-05-07
申请号：US11921651
申请日：2006-06-12
IPC分类号： G06F3/038
CPC分类号： G09G3/3688
摘要： The subject invention provides a drive circuit for a display apparatus, comprising: a shift register; and a pulse generation circuit for generating a drive pulse signal using an output pulse signal generated in the shift register, wherein: the pulse generation circuit forms a pulse-starting edge and a pulse-termination edge of the drive pulse signal using a rise or a fall of pulse resulting from activation of the output pulse signal. On this account, pulse generation can be performed with high accuracy in a pulse generation circuit used for a drive circuit for a display apparatus or the like.
摘要翻译： 本发明提供了一种用于显示装置的驱动电路，包括：移位寄存器; 以及脉冲发生电路，用于使用在所述移位寄存器中产生的输出脉冲信号来产生驱动脉冲信号，其中：所述脉冲发生电路使用上升沿或者相对的方向形成所述驱动脉冲信号的脉冲起始边沿和脉冲终止边沿 由于输出脉冲信号的激活而产生的脉冲下降。 因此，在用于显示装置的驱动电路等的脉冲发生电路中，可以高精度地进行脉冲发生。
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公开(公告)号：US07420402B2
公开(公告)日：2008-09-02
申请号：US11043178
申请日：2005-01-27
IPC分类号： H03K3/356
CPC分类号： H03K3/356165 , G09G3/3677 , G09G3/3688 , G11C19/00 , H03K3/012 , H03K3/356113 , H03K3/356147
摘要： A latch section includes a latch circuit. The latch circuit includes inverters and latches an input signal from a gating section. Between one of the inverters of the latch circuit and the output terminal OUT is disposed an analog switch whose ON/OFF characteristics are switched according to High/Low of a reset signal. Between the output terminal and an input for receiving a low potential as a power supply of a flip-flop is disposed a switching element whose ON/OFF characteristics are switched according to High/Low of the reset signal.
摘要翻译： 锁存部分包括锁存电路。 锁存电路包括反相器并锁存来自门控部分的输入信号。 在锁存电路的一个反相器和输出端子OUT之间设置有根据复位信号的高/低切换开/关特性的模拟开关。 在输出端子和用于接收作为触发器的电源的低电位的输入端之间设置有根据复位信号的高/低切换开/关特性的开关元件。
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公开(公告)号：US08970565B2
公开(公告)日：2015-03-03
申请号：US13378233
申请日：2010-03-18
CPC分类号： G11C19/28 , G09G3/3677 , G09G2310/063
摘要： A stage of the shift register has (i) a set-reset type flip-flop which receives an initialization signal and (ii) a signal generating circuit which receives a simultaneous selection signal and which generates an output signal by use of an output of the flip-flop. In at least one example embodiment, the output of the flip-flop becomes inactive regardless of whether a setting signal and a resetting signal are active or inactive, as long as the initialization signal is active. The initialization signal becomes active before the end of the simultaneous selection, and then becomes inactive after the end of the simultaneous selection. This makes it possible to stabilize operation of the shift register after the end of simultaneous selection of a plurality of signal lines carried out by the display driving circuit at a predetermined timing.
摘要翻译： 移位寄存器的一级具有（i）接收初始化信号的设置复位型触发器，以及（ii）接收同时选择信号并且通过使用输出信号产生输出信号的信号发生电路 拖鞋。 在至少一个示例性实施例中，只要初始化信号有效，触发器的输出就会变得无效，而不管设置信号和复位信号是有效还是无效。 初始化信号在同时选择结束之前变为有效，然后在同时选择结束后变为无效。 这使得可以在预定定时同时选择由显示驱动电路执行的多条信号线结束之后稳定移位寄存器的操作。
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74.发明授权Signal processing circuit, inverter circuit, buffer circuit, level shifter, flip-flop, driver circuit, and display device 有权信号处理电路，逆变电路，缓冲电路，电平转换器，触发器，驱动电路和显示装置公开(公告)号：US08779809B2
公开(公告)日：2014-07-15
申请号：US13819400
申请日：2011-08-31
IPC分类号： H03K3/00
CPC分类号： H02J4/00 , H03K3/356008 , H03K3/356026 , H03K19/01714 , H03K19/01735 , Y10T307/50
摘要： A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; and an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal, the electric charge control section and the first output section being connected to each other via a relay section for either electrically connecting the electric charge control section and the first output section to each other or electrically blocking the electric charge control section and the first output section from each other, the electric charge control section including a resistor connected to a second power source. This configuration can increase reliability of a bootstrap-type signal processing circuit.
摘要翻译： 本发明的信号处理电路包括：第一和第二输入端; 输出端子; 自举电容器; 与第二输入端子和输出端子连接的第一输出部分; 连接到第一输入端子的第二输出部分，第一电源和输出端子; 以及用于控制自举电容器的电荷的电荷控制部分，所述电荷控制部分连接到所述第一输入端子，所述电荷控制部分和所述第一输出部分经由继电器部分彼此连接，用于任一 将电荷控制部和第一输出部彼此电连接，或者将电荷控制部和第一输出部彼此电阻塞，电荷控制部包括与第二电源连接的电阻。 该配置可以增加自举式信号处理电路的可靠性。
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75.发明授权Display driving circuit having a memory circuit, display device, and display driving method 有权具有存储电路，显示装置和显示驱动方法的显示驱动电路公开(公告)号：US08547368B2
公开(公告)日：2013-10-01
申请号：US12734363
申请日：2008-09-02
CPC分类号： G09G3/3677 , G09G3/3655 , G09G2300/0876 , G09G2310/0286 , G09G2310/08 , G09G2320/0219 , G11C19/184
摘要： A display driving circuit of the present invention includes: a source driver (20) which outputs a source signal; a gate driver (30) which outputs a gate signal for turning on a switching element on a row; and a CS driver (40) which outputs a CS signal (CSOUT) whose electric potential is switched in a predetermined direction (low to high or high to low) in accordance with a polarity of the source signal. A CS driver (CSn) on an n-th row outputs a CS signal (CSOUT) to the n-th row in accordance with a gate signal (GLn) for the n-th row outputted from a gate driver (Gn) provided on the n-th row. This makes it possible to provide a display driving circuit which enables CC driving with a simple configuration.
摘要翻译： 本发明的显示驱动电路包括：源极驱动器，其输出源极信号; 栅极驱动器（30），其输出用于导通行上的开关元件的栅极信号; 以及CS驱动器（40），其根据源极信号的极性输出电位从规定的方向（低到高或高到低）切换的CS信号（CSOUT）。 第n行的CS驱动器（CSn）根据从设置在第n行的栅极驱动器（Gn）输出的第n行的栅极信号（GLn）向第n行输出CS信号（CSOUT） 第n行。 这使得可以提供一种能够以简单的结构实现CC驱动的显示驱动电路。
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76.发明申请SIGNAL PROCESSING CIRCUIT, INVERTER CIRCUIT, BUFFER CIRCUIT, DRIVER CIRCUIT, LEVEL SHIFTER, AND DISPLAY DEVICE 有权信号处理电路，逆变器电路，缓冲电路，驱动电路，电平变换器和显示装置公开(公告)号：US20130194033A1
公开(公告)日：2013-08-01
申请号：US13819043
申请日：2011-08-31
IPC分类号： G05F3/16
CPC分类号： G05F3/16 , G09G3/3674 , G09G2310/0286 , G09G2310/0291 , H04L25/0272
摘要： A signal processing circuit of the present invention includes: first and second input terminals; an output terminal; a bootstrap capacitor; a first output section connected to the second input terminal and the output terminal; a second output section connected to the first input terminal, a first power source, and the output terminal; an electric charge control section for controlling the electric charge of the bootstrap capacitor, the electric charge control section being connected to the first input terminal; and a resistor having (i) a first end connected to the output terminal and (ii) a second end connected to a second power source. This arrangement allows the signal processing circuit to maintain an output potential even after a bootstrap effect has worn off.
摘要翻译： 本发明的信号处理电路包括：第一和第二输入端; 输出端子; 自举电容器; 与第二输入端子和输出端子连接的第一输出部分; 连接到第一输入端子的第二输出部分，第一电源和输出端子; 用于控制所述自举电容器的电荷的电荷控制部分，所述电荷控制部分连接到所述第一输入端子; 以及电阻器，其具有（i）连接到所述输出端子的第一端和（ii）连接到第二电源的第二端。 这种布置允许信号处理电路即使在自举效应已经磨损之后仍然保持输出电位。
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公开(公告)号：US20130169319A1
公开(公告)日：2013-07-04
申请号：US13819827
申请日：2011-08-31
IPC分类号： H03K17/00
CPC分类号： H03K17/005 , G09G3/3677 , G09G2310/0286 , G09G2310/08 , G11C19/184 , G11C19/28 , H03K19/00315
摘要： A signal processing circuit of the present invention includes: a first input terminal; a second input terminal; a third input terminal; a first node; a second node; an output terminal; a resistor; a first signal generating section which (i) is connected to the first node, a third input terminal, and the output terminal and (ii) includes a bootstrap capacitor; and a second signal generating section which is connected to the second node, a first power supply, and the output terminal. The first node becomes active in a case where the first input terminal becomes active. The second node becomes active in a case where the second input terminal becomes active. The output terminal is connected to the first power supply via the resistor. With the configuration, it is possible to have an improvement in operational stability of the signal processing circuit.
摘要翻译： 本发明的信号处理电路包括：第一输入端; 第二输入端; 第三输入端; 第一个节点; 第二个节点; 输出端子; 一个电阻; （i）连接到第一节点的第一信号产生部分，第三输入端子和输出端子，以及（ii）包括自举电容器; 以及连接到第二节点的第二信号产生部分，第一电源和输出端子。 在第一输入端子变为活动状态的情况下，第一节点变为活动状态。 在第二输入端子变为活动状态的情况下，第二节点变为活动状态。 输出端子通过电阻连接到第一个电源。 利用该配置，可以改善信号处理电路的操作稳定性。
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78.发明授权Signal output circuit, shift register, output signal generating method, display device driving circuit, and display device 有权信号输出电路，移位寄存器，输出信号生成方法，显示装置驱动电路和显示装置公开(公告)号：US08344988B2
公开(公告)日：2013-01-01
申请号：US11922345
申请日：2006-07-13
IPC分类号： G09G3/36
摘要： A signal output circuit of one embodiment of the present invention is provided in a unit stage of a shift register. The signal output circuit includes a set-reset flip-flop, and a signal generation circuit for generating an output signal by loading or blocking a clock signal in accordance with a signal inputted thereto. The signal output circuit is arranged such that: the signal generation circuit receives a signal outputted from the flip-flop and the output signal fed back to the signal generating circuit; and the output signal is fed back to a reset input of the flip-flop. This makes it possible to achieve a reduction in the area of the circuit and a simplification of the circuit.
摘要翻译： 本发明的一个实施例的信号输出电路设置在移位寄存器的单元级中。 信号输出电路包括设置复位触发器和信号产生电路，用于根据输入的信号通过加载或阻塞时钟信号来产生输出信号。 信号输出电路被布置为：信号发生电路接收从触发器输出的信号和反馈到信号发生电路的输出信号; 并将输出信号反馈到触发器的复位输入。 这使得可以实现电路面积的减小和电路的简化。
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公开(公告)号：US08223112B2
公开(公告)日：2012-07-17
申请号：US12734234
申请日：2008-08-18
CPC分类号： G11C19/28 , G09G3/20 , G09G3/3266 , G09G3/3275 , G09G3/3648 , G09G3/3674 , G09G3/3677 , G09G3/3685 , G09G3/3688 , G09G2300/0426 , G09G2310/0245 , G09G2310/0267 , G09G2310/0275 , G09G2310/0286 , G09G2310/0291
摘要： At least one embodiment of the present invention is directed to, even when external noise is applied to a shift register during all-on operation, preventing through-current from flowing in unit circuits and also to prevent increase in load on all-on control signal lines. When a high-level all-on control signal is provided to a unit circuit of a shift register, a transistor T3 is brought into off-state, so that a transistor T2 cannot output an on-voltage to a first output terminal. However, a transistor T24 is brought into on-state, so that the first output terminal outputs an on-voltage to the exterior. On the other hand, a transistor T32 is brought into on-state, so that a second output terminal outputs an off-voltage to a unit circuit 11 in the next stage. At this time, the transistor T3 is kept in off-state, so that no through-current flows to the transistors T24 and T3.
摘要翻译： 本发明的至少一个实施例涉及即使当在全导通操作期间外部噪声被施加到移位寄存器时，也可以防止在单位电路中流过电流，并且还防止全通控制信号的负载增加 线条。 当向移位寄存器的单元电路提供高电平全通控制信号时，晶体管T3进入截止状态，晶体管T2不能向第一输出端子输出导通电压。 然而，晶体管T24进入导通状态，使得第一输出端子向外部输出导通电压。 另一方面，晶体管T32进入导通状态，使得第二输出端在下一级向单元电路11输出截止电压。 此时，晶体管T3保持截止状态，使得没有贯通电流流向晶体管T24和T3。
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公开(公告)号：US20100309184A1
公开(公告)日：2010-12-09
申请号：US12734595
申请日：2008-08-20
CPC分类号： G09G3/3677 , G09G2300/0408 , G09G2300/0426 , G09G2310/0289 , G11C19/28 , H01L27/124 , H03K17/161 , H03K17/162 , H03K17/687
摘要： A circuit which is constituted by a plurality of n-channel transistors includes, in at least one embodiment, a transistor (T1) which has a drain terminal to which an input signal is supplied and a source terminal from which a output signal is supplied; and a transistor (T2) which has a drain terminal to which a control signal is supplied and a source terminal connected to a gate terminal of the transistor (T1). A gate terminal of the transistor (T2) is connected to the source terminal of the transistor (T2). With the arrangement, it is possible to provide (i) a semiconductor device which is constituted by transistors having an identical conductivity type and which is capable of reducing an influence of noise, and (ii) a display device including the semiconductor device.
摘要翻译： 在至少一个实施例中，由多个n沟道晶体管构成的电路包括具有供给输入信号的漏极端子和提供输出信号的源极端子的晶体管（T1）; 以及具有提供控制信号的漏极端子和与晶体管（T1）的栅极端子连接的源极端子的晶体管（T2）。 晶体管（T2）的栅极端子连接到晶体管（T2）的源极端子。 通过该结构，可以提供（i）由具有相同导电类型并能够减小噪声影响的晶体管构成的半导体器件，以及（ii）包括半导体器件的显示器件。
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