公开(公告)号：US20090010039A1

公开(公告)日：2009-01-08

申请号：US12132972

申请日：2008-06-04

申请人： Naoya Tokiwa ,  Kazushige Kanda ,  Toshiaki Edahiro ,  Koji Hosono ,  Takuya Futatsuyama ,  Shigeo Ohsima

发明人： Naoya Tokiwa ,  Kazushige Kanda ,  Toshiaki Edahiro ,  Koji Hosono ,  Takuya Futatsuyama ,  Shigeo Ohsima

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2013/0092 ,  G11C2213/32 ,  G11C2213/72

摘要： According to one embodiment, a nonvolatile memory device includes: a memory cell array including memory cells each having a variable resistance element for nonvolatilely storing data identified by an electrically rewritable resistance value; a first data latch storing write and erase data to be written on a given group of memory cells of the memory cell array for a write and erase operation; and a second data latch storing reference data for performing a compensation operation of the given group to compensate write and erase disturbance accompanied by the write or erase operation.

摘要翻译： 根据一个实施例，非易失性存储器件包括：存储单元阵列，其包括各自具有用于非易失性地存储由电可重写电阻值识别的数据的可变电阻元件的存储单元; 存储要写入存储单元阵列的给定组的存储单元的用于写入和擦除操作的写入和擦除数据的第一数据锁存器; 以及第二数据锁存器，存储用于执行给定组的补偿操作以补偿伴随着写入或擦除操作的写入和擦除干扰的参考数据。

公开(公告)号：US20080291716A1

公开(公告)日：2008-11-27

申请号：US12123827

申请日：2008-05-20

申请人： Takuya Futatsuyama ,  Koji Hosono ,  Toshiaki Edahiro ,  Naoya Tokiwa ,  Kazushige Kanda ,  Shigeo Ohshima

发明人： Takuya Futatsuyama ,  Koji Hosono ,  Toshiaki Edahiro ,  Naoya Tokiwa ,  Kazushige Kanda ,  Shigeo Ohshima

IPC分类号： G11C11/00

CPC分类号： G11C11/36

摘要： A method of programming a non-volatile memory device with memory cells formed of variable resistance elements and disposed between word lines and bit lines, includes: previously charging a selected word line and a selected bit line together with a non-selected word line and a non-selected bit line up to a certain voltage; and further charging the selected word line and the non-selected bit line up to a program voltage higher than the certain voltage and a program-block voltage, respectively, and simultaneously discharging the selected bit line.

摘要翻译： 一种使用由可变电阻元件形成并且设置在字线和位线之间的存储单元来编程非易失性存储器件的方法包括：预先对所选择的字线和所选择的位线以及未选择的字线和 非选择位线达到一定电压; 并且进一步对所选字线和未选择的位线进行充电，直到分别高于特定电压和编程块电压的编程电压，并同时对所选择的位线进行放电。

公开(公告)号：US20080239812A1

公开(公告)日：2008-10-02

申请号：US12058356

申请日：2008-03-28

申请人： Naofumi ABIKO ,  Takuya Futatsuyama

发明人： Naofumi ABIKO ,  Takuya Futatsuyama

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5634 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： According to an embodiment, a nonvolatile semiconductor memory system includes: a nonvolatile semiconductor memory; and a memory controller having: a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data between the nonvolatile semiconductor memory; a memory that stores writing information indicating a memory cell transistor that is written the latest in each of the NAND cell units; and a processor that sets a read voltage based on the writing information to readout data from the memory cell transistors connected to a first word line; wherein a row controller is configured to set a plurality of levels of the read voltage to be applied to the first word line, with respect to one threshold for discriminating data stored in a memory cell transistors.

摘要翻译： 根据实施例，非易失性半导体存储器系统包括：非易失性半导体存储器; 以及存储器控制器，具有：存储器接口单元，其向非易失性半导体存储器输入命令并在非易失性半导体存储器之间输入或输出数据; 存储器，其存储表示在每个NAND单元单元中写入最新的存储单元晶体管的写入信息; 以及处理器，其基于写入信息将读取电压设置为从连接到第一字线的存储单元晶体管的读出数据; 其中行控制器被配置为相对于用于识别存储在存储单元晶体管中的数据的一个阈值来设置要施加到第一字线的读取电压的多个电平。

公开(公告)号：US20080043531A1

公开(公告)日：2008-02-21

申请号：US11849891

申请日：2007-09-04

申请人： Yasushi KAMEDA ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawai

发明人： Yasushi KAMEDA ,  Ken Takeuchi ,  Hitoshi Shiga ,  Takuya Futatsuyama ,  Koichi Kawai

IPC分类号： G11C16/06

CPC分类号： G11C16/102

摘要： The non-volatile semiconductor memory device has a circuit which maintains and holds the potentials of bit lines, and either ones of even-bit lines or odd-bit lines are connected to the circuit. When the bit line potential holding circuit is connected to even-bit lines and a block copy is performed, data is first outputted to the even-bit lines, and after the potential of the even-bit line is determined, the bit line potential holding circuit operates. Then, biasing of the potential of the even-bit lines is carried out by the bit line potential holding circuit, the potentials of the bit lines are maintained and held. At the same time, data is outputted to the odd-bit lines and the potentials of the odd-bit lines are determined. Then, a program voltage is supplied to a selected word line, and data is simultaneously written (programmed) in the memory cells connected to the even-bit lines, and the memory cells connected to the odd-bit lines.

摘要翻译： 非易失性半导体存储器件具有维持并保持位线的电位的电路，偶数位线或奇数位线中的任一个与电路连接。 当位线电位保持电路连接到偶数位线并执行块复制时，首先将数据输出到偶数位线，并且在确定偶数位线的电位之后，位线电位保持 电路工作。 然后，通过位线电位保持电路来执行偶数位线的电位的偏置，保持并保持位线的电位。 同时，将数据输出到奇数位线，并且确定奇数位线的电位。 然后，将编程电压提供给所选择的字线，并且数据被同时写入（编程）到连接到偶数位线的存储器单元中，并且存储器单元连接到奇数位线。

公开(公告)号：US07177173B2

公开(公告)日：2007-02-13

申请号：US11407146

申请日：2006-04-20

申请人： Takuya Futatsuyama

发明人： Takuya Futatsuyama

IPC分类号： G11C5/06

CPC分类号： G11C16/0483 ,  G11C16/16

摘要： A semiconductor device includes a memory cell array, word lines, a selector, driving lines and transfer transistors. The memory cell array includes electrically rewritable nonvolatile memory cells. The word lines are commonly connected to memory cells arranged in the same row. The selector configured to select memory cells corresponding to the plurality of word lines in the array. Each driving line is corresponding to one of the word lines. Transfer transistors selectively connect one of the word lines and one of the driving lines. A first word line is connected to a first control gate, a second word line next to the first word line connect to a second control gate, and a third word line next to the second word line connected to a third control gate which is arranged next to first control gate.

摘要翻译： 半导体器件包括存储单元阵列，字线，选择器，驱动线和转移晶体管。 存储单元阵列包括电可重写的非易失性存储单元。 字线通常连接到排列在同一行中的存储单元。 所述选择器被配置为选择与所述阵列中的所述多个字线相对应的存储单元。 每条驱动线对应于一条字线。 传输晶体管选择性地连接字线和其中一条驱动线。 第一字线连接到第一控制栅极，连接到第二控制栅极的第一字线旁边的第二字线和与第三控制栅极连接的第二字线相邻的第三字线 先控制门。

公开(公告)号：US07173862B2

公开(公告)日：2007-02-06

申请号：US11138427

申请日：2005-05-27

申请人： Takuya Futatsuyama ,  Kenichi Imamiya ,  Koji Hosono ,  Noboru Shibata

发明人： Takuya Futatsuyama ,  Kenichi Imamiya ,  Koji Hosono ,  Noboru Shibata

IPC分类号： G11C16/04

CPC分类号： G11C16/3445 ,  G11C16/04 ,  G11C16/16 ,  G11C16/3436 ,  G11C16/3459 ,  G11C29/50004

摘要： After execution of sub-block erase (S2) for partly erasing a memory cell block, sub-block erase verify read is executed (S4). As a result of the sub-block erase verify read, if the sub-block erase is completed, then terminate the sub-block erase (S5). If otherwise the sub-block erase is not completed yet, then perform over-program verify read (S6) to thereby determine whether the cause of an event that a sub-block erase-verify result becomes “Fail” due to the deficiency of erase or the presence of an over-programmed cell or cells. If the result of such over-program verify read is “Pass,” then repeat execution of the sub-block erase verify read (S2). When the over-program verify read (S6) is “Fail,” output a Fail result and then complete the operation (S8).

摘要翻译： 在执行用于部分擦除存储单元块的子块擦除（S 2）之后，执行子块擦除验证读取（S 4）。 作为子块擦除验证读取的结果，如果子块擦除完成，则终止子块擦除（S 5）。 否则子块擦除尚未完成，则执行过程编程验证读取（S 6），从而确定子块擦除验证结果由于不足而导致的“失败”事件的原因 擦除或过度编程的细胞或细胞的存在。 如果这种过程编程验证读取的结果为“通过”，则重复执行子块擦除验证读取（S 2）。 当过程程序验证读取（S 6）为“失败”时，输出失败结果，然后完成操作（S 8）。

公开(公告)号：US20060274565A1

公开(公告)日：2006-12-07

申请号：US11277706

申请日：2006-03-28

申请人： Daisaburo Takashima ,  Shuso Fujii ,  Takuya Futatsuyama ,  Takaya Suda ,  Masaki Momodomi

发明人： Daisaburo Takashima ,  Shuso Fujii ,  Takuya Futatsuyama ,  Takaya Suda ,  Masaki Momodomi

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  G06F12/0246 ,  G06F12/0292 ,  G06F2212/2022 ,  G06F2212/7201 ,  G11C8/10

摘要： A memory system includes a ferroelectric memory, flash EEPROM, control circuit, and interface circuit. The control circuit is configured to control the ferroelectric memory and flash EEPROM. The interface circuit is configured to communicate externally. Data is programmed in the flash EEPROM by a write unit which is smaller than a block as an erase unit and larger than a page as a program unit. The ferroelectric memory stores a logical address-physical address conversion table using the write unit.

摘要翻译： 存储系统包括铁电存储器，闪存EEPROM，控制电路和接口电路。 控制电路被配置为控制铁电存储器和闪存EEPROM。 接口电路被配置为从外部通信。 数据通过写入单元编程在闪存EEPROM中，该写入单元比作为擦除单元的块小并且大于作为程序单元的页面。 铁电存储器使用写入单元存储逻辑地址 - 物理地址转换表。

公开(公告)号：US07099193B2

公开(公告)日：2006-08-29

申请号：US10934626

申请日：2004-09-07

申请人： Takuya Futatsuyama

发明人： Takuya Futatsuyama

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C5/14 ,  G11C8/00

CPC分类号： G11C16/0483 ,  G11C16/3418

摘要： A nonvolatile semiconductor memory device includes a NAND cell with a plurality of electrically data rewritable memory cells being connected in series, word lines connected to control gates of the memory cells, a common source line connectable to one end of the NAND cell, a bit line connectable to a remaining end of the NAND cell, and a word line control circuit. The word line control circuit supplies a word line of a selected memory cell with a write voltage for writing data into this memory cell, supplies a word line of a memory cell located on the common source line side by N (N is an integer greater than or equal to 2) cells from the selected memory cell with a reference voltage for causing this memory cell to cut off, supplies an auxiliary voltage less than the write voltage to respective word lines of N−1 memory cells located between the selected memory cell and the memory cell at the position of the N cells, and supplies to word lines of remaining memory cells an intermediate voltage between the write voltage and the reference voltage.

摘要翻译： 非易失性半导体存储器件包括具有串联连接的多个电数据可重写存储单元的NAND单元，连接到存储单元的控制栅极的字线，可连接到NAND单元的一端的公共源极线，位线 可连接到NAND单元的剩余端，以及字线控制电路。 字线控制电路将选择的存储单元的字线用于将数据写入该存储单元的写入电压，将位于公共源极线侧的存储单元的字线提供N（N是大于 或等于2）具有用于使该存储单元断开的参考电压的所选存储单元的单元，将小于写入电压的辅助电压提供给位于所选择的存储单元与所选存储单元之间的N-1个存储单元的各个字线 在N个单元的位置处的存储单元，并且向剩余存储单元的字线提供写入电压和参考电压之间的中间电压。

公开(公告)号：US20050105334A1

公开(公告)日：2005-05-19

申请号：US10934626

申请日：2004-09-07

申请人： Takuya Futatsuyama

发明人： Takuya Futatsuyama

IPC分类号： H01L21/8247 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  H01L27/10 ,  H01L27/115

CPC分类号： G11C16/0483 ,  G11C16/3418

摘要： A nonvolatile semiconductor memory device includes a NAND cell with a plurality of electrically data rewritable memory cells being connected in series, word lines connected to control gates of the memory cells, a common source line connectable to one end of the NAND cell, a bit line connectable to a remaining end of the NAND cell, and a word line control circuit. The word line control circuit supplies a word line of a selected memory cell with a write voltage for writing data into this memory cell, supplies a word line of a memory cell located on the common source line side by N (N is an integer greater than or equal to 2) cells from the selected memory cell with a reference voltage for causing this memory cell to cut off, supplies an auxiliary voltage less than the write voltage to respective word lines of N-1 memory cells located between the selected memory cell and the memory cell at the position of the N cells, and supplies to word lines of remaining memory cells an intermediate voltage between the write voltage and the reference voltage.

摘要翻译： 非易失性半导体存储器件包括具有串联连接的多个电数据可重写存储单元的NAND单元，连接到存储单元的控制栅极的字线，可连接到NAND单元的一端的公共源极线，位线 可连接到NAND单元的剩余端，以及字线控制电路。 字线控制电路将选择的存储单元的字线用于将数据写入该存储单元的写入电压，将位于公共源极线侧的存储单元的字线提供N（N是大于 或等于2）具有用于使该存储单元断开的参考电压的所选存储单元的单元，将小于写入电压的辅助电压提供给位于所选择的存储单元与所选存储单元之间的N-1个存储单元的各个字线 在N个单元的位置处的存储单元，并且向剩余存储单元的字线提供写入电压和参考电压之间的中间电压。

公开(公告)号：US08625349B2

公开(公告)日：2014-01-07

申请号：US12618200

申请日：2009-11-13

申请人： Hiroyuki Kutsukake ,  Kenji Gomikawa ,  Mitsuhiro Noguchi ,  Kikuko Sugimae ,  Masato Endo ,  Takuya Futatsuyama ,  Koji Kato ,  Kanae Uchida

发明人： Hiroyuki Kutsukake ,  Kenji Gomikawa ,  Mitsuhiro Noguchi ,  Kikuko Sugimae ,  Masato Endo ,  Takuya Futatsuyama ,  Koji Kato ,  Kanae Uchida

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/16 ,  H01L27/11521 ,  H01L27/11526

摘要： A memory includes a first word line which is connected to a control gate electrode of a first memory cell, a second word line which is connected to a control gate electrode of a second memory cell, a potential transfer line which is connected to both of the first and second word lines, a first N-channel MOS transistor which is connected between the first word line and the potential transfer line, and a second N-channel MOS transistor which is connected between the second word line and the potential transfer line. A control circuit supplies a first potential with a plus value to a semiconductor substrate, and supplies a second potential with the plus value lower than the first potential to the potential transfer line, to turn the first N-channel MOS transistor on, and to turn the second N-channel MOS transistor off, in erasing data of the first memory cell.

摘要翻译： 存储器包括连接到第一存储单元的控制栅电极的第一字线，连接到第二存储单元的控制栅极的第二字线，连接到第二存储单元的控制栅电极的电位传输线 第一和第二字线，连接在第一字线和电位传输线之间的第一N沟道MOS晶体管和连接在第二字线和电位传输线之间的第二N沟道MOS晶体管。 控制电路向半导体衬底提供具有正值的第一电位，并向电位传输线提供具有低于第一电位的正值的第二电位，以使第一N沟道MOS晶体管导通，并转向 第二N沟道MOS晶体管截止，以擦除第一存储单元的数据。