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公开(公告)号:US20230116391A1
公开(公告)日:2023-04-13
申请号:US17852304
申请日:2022-06-28
Applicant: Microchip Technology Inc.
Inventor: Aaron Severance , Jonathan W. Greene , Joel Vandergriendt
IPC: G06F9/30
Abstract: A method and apparatus for embedding a microprocessor in a programmable logic device (PLD), where the microprocessor has a logic unit that can operate in two modes. A first mode is a general purpose mode running at least one general purpose process related to the PLD, and a second mode is a fixed function mode emulating a fixed function for use by logic configured into a fabric of the PLD (fabric). A memory unit is coupled to the logic unit and to the fabric, and the fabric is operable for transferring signals with the logic unit in relation to the fixed function.
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公开(公告)号:US20220188604A1
公开(公告)日:2022-06-16
申请号:US17347388
申请日:2021-06-14
Applicant: Microchip Technology Inc.
Inventor: Lorenzo Zuolo , Rino Micheloni
Abstract: A method for performing a neural network operation includes receiving weight and bias values of a deep neural network (DNN). An array of feature values, a bias value and a set of weight values for a single layer of the DNN are coupled to a neural network engine. Multiply-and-accumulate operations are performed on the single layer at one or more multiply and accumulate circuit (MAC) to obtain a sum corresponding to each neuron in the single layer. A layer output value corresponding to each neuron in the single layer is coupled to a corresponding input of the MAC. The coupling a bias value and a set of weight values, the performing multiply-and-accumulate operations and the coupling a layer output value are repeated to generate an output-layer-sum corresponding to each output-layer neuron and an activation function is performed on each output-layer-sum to generate DNN output values.
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公开(公告)号:US20220165348A1
公开(公告)日:2022-05-26
申请号:US17213675
申请日:2021-03-26
Applicant: Microchip Technology Inc.
Inventor: Lorenzo Zuolo , Rino Micheloni
Abstract: A method and apparatus for determining when actual wear of a flash memory device differs from a reliability state. Configuration files of a reliability-state classification neural network model are stored. The operation of a flash memory device is monitored to identify current physical characteristic values. A read of the flash memory device is performed to determine a number of errors. A neural network operation is performed using as input a set of threshold voltage shift offset values currently being used to perform reads of the flash memory device and the calculated number of errors, to identify a predicted reliability state. The identified current physical characteristic values are compared to corresponding tags associated with the predicted reliability state and a flag or other indication is stored when the comparison indicates that the identified current physical characteristic values do not correspond to the respective tags associated with the predicted reliability state.
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74.
公开(公告)号:US11245391B2
公开(公告)日:2022-02-08
申请号:US16933983
申请日:2020-07-20
Applicant: Microchip Technology Inc.
Inventor: Isaac Ko , Ka Wai Ho , Wan Tim Chan , Jimes Lei
IPC: H03K17/06 , A61B8/00 , H03K17/693
Abstract: Described herein are multiple designs for an improved analog switch for use in transmitting high voltage signals without using high voltage power supplies for the switch. The analog switches are able to pass and block input signals in the approximate range of −100 V to +100 V. The use of translinear loops and a bootstrap configuration results in a constant on-resistance of the symmetrical switches and matches the conductance of each analog switch to the transconductance of an NMOS transistor, which can be easily stabilized with a constant gm biasing scheme. In certain embodiments, a shunt termination (T-switch) configuration is used for better off-isolation, and each of the symmetrical switches has its own translinear loop and thus flexibility of on-resistance and termination voltage.
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公开(公告)号:US20220029778A1
公开(公告)日:2022-01-27
申请号:US17242493
申请日:2021-04-28
Applicant: Microchip Technology Inc.
Inventor: Atanu Chattopadhyay , Andras de Koos
IPC: H04L7/00
Abstract: System and method for synchronizing a plurality of nodes to a timing signal using a daisy-chain network having a forward transmission path and a reverse transmission path connected at a midpoint. Latency of the timing signal to the midpoint of the daisy-chain network is determined, a respective latency of the timing signal from the node to the midpoint of the daisy-chain network is determined, and a respective timing offset for each of the plurality of nodes is calculated. A local time-of-day counter at each of the plurality of nodes is adjusted based upon the respective timing offset of the node to synchronize the plurality of nodes to the timing signal.
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公开(公告)号:US11221236B1
公开(公告)日:2022-01-11
申请号:US16927553
申请日:2020-07-13
Applicant: Microchip Technology Inc.
Inventor: Ganesh Shaga , Kevin Mark Smith, Jr. , Hwangsoo Choi , Sudheer Puttapudi
IPC: G01D5/20
Abstract: An angular position sensor comprising two planar excitation coils forming a substantially circular interior area and two planar sensing coils positioned within a minor sector of the substantially circular interior area. Each of the two planar sensing coils comprises a clockwise winding portion and a counter-clockwise winding portion. The angular position sensor further comprises a substantially circular rotatable inductive coupling element positioned in overlying relation to the two planar sensing coils and separated from the two planar sensing coils by an airgap, wherein the substantially circular rotatable inductive coupling element comprises three, substantially evenly space, sector apertures.
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公开(公告)号:US20210225645A1
公开(公告)日:2021-07-22
申请号:US16785491
申请日:2020-02-07
Applicant: Microchip Technology Inc.
Inventor: Amaury Gendron-Hansen , Bruce Odekirk
IPC: H01L21/02 , H01L21/04 , H01L21/67 , H01L27/092
Abstract: A method for fabricating a silicon carbide semiconductor device includes providing a SiC epitaxial layer disposed over a surface of a SiC substrate, forming an implant aperture in a hardmask layer on a surface of the expitaxial SiC layer, implanting contact and well regions in the SiC epitaxial layer through the hardmask layer, the contact region lying completely within and recessed from edges of the well region by performing one of implanting the well region through the implant aperture, reducing the area of the implant aperture forming a reduced-area contact implant aperture and implanting the contact region through the reduced-area implant aperture to form a contact region, and implanting the contact region through the implant aperture, increasing the area of the implant aperture to form a increased-area well implant aperture and implanting the well region through the increased-area implant aperture to form a well region completely surrounding the contact region.
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公开(公告)号:US20210194488A1
公开(公告)日:2021-06-24
申请号:US16827691
申请日:2020-03-23
Applicant: Microchip Technology Inc.
Inventor: Mike Willingham
Abstract: A circuit for correcting phase interpolator rollover integral non-linearity errors includes a rollover detector circuit for detecting when an interpolator rollover event of a phase integer portion of a phase interpolator has occurred, and a correction circuit that adds a signed predistortion correction to the VCO clock cycle fraction value of the phase interpolator when the rollover detector circuit has detected the interpolator rollover event.
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79.
公开(公告)号:US20210124641A1
公开(公告)日:2021-04-29
申请号:US16678810
申请日:2019-11-08
Applicant: Microchip Technology Inc.
Inventor: Robert E. Caldwell, JR.
Abstract: A method for operating a storage controller to write to a group of multi-actuator disk drives includes receiving a data stream, performing RAID mapping to a preselected RAID level, organizing the data stream into at least one data stream, creating at least one parity data stream, organizing each data stream and parity data stream into blocks of data, dividing each data stream and each parity data stream into groups of blocks of data assigned to a logical unit representing a drive and an actuator, blocks of data from a data stream and parity stream assigned to a different drive, sequential groups of blocks of data assigned substantially equally to logical units representing actuators in each drive, providing each group of blocks of data to a target port associated with the drive to which it has been assigned, and sending each group of blocks of data from the target port.
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公开(公告)号:US20210111082A1
公开(公告)日:2021-04-15
申请号:US16816010
申请日:2020-03-11
Applicant: Microchip Technology Inc.
Inventor: Matthias Klein , Andreas Zakrzewski , Richard Gruenwald
Abstract: A packaged electronic die having a micro-cavity and a method for forming a packaged electronic die. The packaged electronic die includes a photoresist frame secured to the electronic die and extending completely around the device. The photoresist frame is further secured to a first major surface of a substrate so as to form an enclosure around the device. Encapsulant material extends over the electronic die and around the sides of the electronic die. The encapsulant material is in contact with the first major surface of the substrate around the entire periphery of the electronic die so as to form a seal around the electronic die.
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