公开(公告)号：US20110148483A1

公开(公告)日：2011-06-23

申请号：US12976587

申请日：2010-12-22

Applicant: Sandor Petenyi

Inventor： Sandor Petenyi

IPC: H03L7/00

CPC classification number: G05F3/30

Abstract: An electronic integrated device may include a signal generation stage arranged to generate a first signal representative of an under voltage lockout logic signal. The signal generation stage may include a voltage divider block arranged to provide an internal reference voltage signal to a bandgap core group based upon a reference signal. The bandgap core group may generate the first signal based upon the internal reference voltage signal. The bandgap core group may further include a first generation module arranged to generate a output regulated reference voltage signal based upon the internal reference voltage signal, and a second generation module arranged to generate the first signal based upon the internal reference voltage signal and a driving signal obtained by a preliminary processing of the internal reference voltage signal by a bandgap core module included within the band gap core group.

Abstract translation: 电子集成装置可以包括信号产生级，被配置为产生表示欠压锁定逻辑信号的第一信号。 信号产生级可以包括分压器块，其被布置为基于参考信号向带隙核心组提供内部参考电压信号。 带隙核心组可以基于内部参考电压信号产生第一信号。 带隙核心组还可以包括第一生成模块，其被布置为基于内部参考电压信号产生输出调节参考电压信号;以及第二生成模块，被布置为基于内部参考电压信号和驱动信号产生第一信号 通过由带隙核心组中包括的带隙核心模块对内部参考电压信号进行预处理获得。

公开(公告)号：US20110006691A1

公开(公告)日：2011-01-13

申请号：US12833280

申请日：2010-07-09

Applicant: Karel BLAHA ,  Jan MILSIMER

Inventor： Karel BLAHA ,  Jan MILSIMER

IPC: H05B37/02 ,  G05F1/10 ,  H02J3/00

CPC classification number: H02M7/217 ,  H02M7/48 ,  H02M2001/007 ,  H05B33/0818 ,  Y10T307/406

Abstract: An embodiment of the invention relates to a voltage converter for supplying a semiconductor light source and having at least an input terminal connected to a power supply reference, namely an AC mains voltage reference, and an output terminal providing a current signal to said semiconductor light source, the converter being also connected to a voltage reference and comprising at least a step-down block inserted between a switching node and to the output terminal and connected to the voltage reference and an input block connected to the input terminal, as well as to a first input node and to a first output node of a control circuit, in turn connected to the switching node and to the voltage reference. The input block is a pre-regulator input block and comprises at least a switching component connected to the input terminal and to a capacitive block, in turn inserted between a second input node of the control circuit and the voltage reference, such a switching component having a control terminal connected to the first output node.

Abstract translation: 本发明的一个实施例涉及一种用于提供半导体光源并且至少具有连接到电源基准的输入端子（即，交流电源电压基准）的电压转换器和向所述半导体光源提供电流信号的输出端子 所述转换器还连接到电压基准，并且至少包括插入在开关节点和输出端子之间的降压块，并连接到电压基准和连接到输入端子的输入块，以及一个 第一输入节点和控制电路的第一输出节点，又连接到开关节点和电压基准。 所述输入块是预调节器输入块，并且至少包括连接到所述输入端和电容块的开关元件，所述开关元件依次插入所述控制电路的第二输入节点与所述电压基准之间，所述开关元件具有 连接到第一输出节点的控制终端。

公开(公告)号：US20100301909A1

公开(公告)日：2010-12-02

申请号：US12787285

申请日：2010-05-25

Applicant: Jaromir Schindler

Inventor： Jaromir Schindler

IPC: H03L7/00

CPC classification number: G05F3/30 ,  H03K17/223 ,  H03K2017/226

Abstract: A startup circuitry connected to a main circuit which has at least an output terminal connected to its feedback terminal by a feedback loop. The startup circuitry is connected to the main circuit in such a manner to break the feedback loop, by having a first circuit node connected to said output terminal of said main circuit and a second circuit node connected to its feedback terminal, said startup circuitry providing a correct output voltage value during the startup phase of said main circuit.

Abstract translation: 连接到主电路的启动电路，其至少具有通过反馈回路连接到其反馈端的输出端子。 启动电路通过使连接到所述主电路的所述输出端的第一电路节点和连接到其反馈端的第二电路节点以断开反馈回路的方式连接到主电路，所述启动电路提供一个 在所述主电路的启动阶段期间校正输出电压值。

公开(公告)号：US07538604B2

公开(公告)日：2009-05-26

申请号：US11655774

申请日：2007-01-19

Applicant: Hynek Saman ,  Peter Murin ,  Martin Boksa ,  Pavel Panus

Inventor： Hynek Saman ,  Peter Murin ,  Martin Boksa ,  Pavel Panus

IPC: H03F1/02

CPC classification number: H03F3/45928 ,  H03F3/45475 ,  H03F2200/459 ,  H03F2203/45136 ,  H03F2203/45166 ,  H03F2203/45522 ,  H03F2203/45528 ,  H03F2203/45534 ,  H03F2203/45586 ,  H03F2203/45591 ,  H03F2203/45601 ,  H03F2203/45616 ,  H03G1/0088

Abstract: A circuit including a first sensitive node, a first component connected between the first sensitive node and a first terminal of a first switch, said first switch controlled by a first control signal variable between a supply voltage level and a second voltage level, and a second switch including a first terminal connected to the first terminal of said first switch, and a second terminal connected to a clean voltage supply, said second switch controlled to connect the first node of said first switch to said clean voltage supply when said first switch is in a non-conducting state.

Abstract translation: 一种电路，包括第一敏感节点，连接在第一敏感节点和第一开关的第一终端之间的第一组件，所述第一开关由在电源电压电平和第二电压电平之间变化的第一控制信号控制， 开关，包括连接到所述第一开关的第一端子的第一端子和连接到清洁电压源的第二端子，所述第二开关被控制为当所述第一开关处于所述第一开关时将所述第一开关的第一节点连接到所述清洁电压源 非导电状态。

公开(公告)号：US20240125930A1

公开(公告)日：2024-04-18

申请号：US18377893

申请日：2023-10-09

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics Design and Application S.R.O. ,  STMicroelectronics (Alps) SAS

Inventor： Robin VASSAL ,  Jiri ANDRLE ,  Peter CABAJ ,  Cyrille TROUILLEAU

IPC: G01S17/08 ,  G01S7/497

CPC classification number: G01S17/08 ,  G01S7/497

Abstract: A method is for detecting one or more objects in a detection zone using a time-of-flight sensor. The method includes emitting optical radiation via the emission circuitry of the sensor and subsequently capturing the reflected optical radiation using the reception circuitry. This captured radiation is quantified in terms of photons, and measurement circuitry determines both the amount of these photons and the distance from the sensor to the object(s). An analysis of the photon count, combined with the calculated distance, is used to determine the presence or absence of objects within the detection zone.

公开(公告)号：US11734221B2

公开(公告)日：2023-08-22

申请号：US17199418

申请日：2021-03-11

Applicant: STMicroelectronics Application GMBH ,  STMICROELECTRONICS DESIGN AND APPLICATION S.R.O.

Inventor： Rolf Nandlinger ,  Radek Olexa

IPC: G06F13/42 ,  G06F9/30 ,  G06F13/16 ,  G06F13/40

CPC classification number: G06F13/4291 ,  G06F9/30134 ,  G06F13/1673 ,  G06F13/4031

Abstract: An embodiment processing system comprises a queued SPI circuit, which comprises a hardware SPI communication interface, an arbiter and a plurality of interface circuits. Each interface circuit comprises a transmission FIFO memory, a reception FIFO memory and an interface control circuit. The interface control circuit is configured to receive first data packets and store them to the transmission FIFO memory. The interface control circuit sequentially reads the first data packets from the transmission FIFO memory, extracts at least one transmission data word, and provides the extracted word to the arbiter. The interface control circuit receives from the arbiter a reception data word and stores second data packets comprising the received reception data word to the reception FIFO memory. The interface control circuit sequentially reads the second data packets from the reception FIFO memory and transmits them to the digital processing circuit.

公开(公告)号：US20230171529A1

公开(公告)日：2023-06-01

申请号：US17537263

申请日：2021-11-29

Applicant: STMICROELECTRONICS DESIGN AND APPLICATION S.R.O.

Inventor： Tomas TEPLY ,  Karel BLAHA

IPC: H04R1/10 ,  H04R9/04 ,  H04R9/06

CPC classification number: H04R1/1025 ,  H04R9/04 ,  H04R9/06 ,  H04R1/1075 ,  H04R2420/07

Abstract: The present disclosure is directed to a device that includes a headphone speaker housing that includes a coil having a first terminal and a second terminal that is configured to operate in a sound generation mode and a battery charging mode. A class D amplifier circuit is configured to rectify in a battery charging mode and amplify in a sound generation mode, the class D amplifier is coupled to the first terminal and the second terminal of the coil. The class D amplifier including a first, second, third, and fourth switch, the first terminal coupled between the first and second switch, the second terminal coupled between the third and fourth switch. An audio generation circuit having a third terminal and a fourth terminal, the third terminal coupled between the first and third switch of the class D amplifier and the fourth terminal coupled between the second and fourth switch of the class D amplifier. A battery charging circuit coupled to the third terminal and the fourth terminal.

公开(公告)号：US20220286319A1

公开(公告)日：2022-09-08

申请号：US17677113

申请日：2022-02-22

Applicant: STMicroelectronics Design and Application S.R.O. ,  STMicroelectronics Application GMBH

Inventor： Fred Rennig ,  Vaclav Dvorak

IPC: H04L12/403 ,  G06F9/30

Abstract: A circuit includes a first and a second memory, a processor and a timer. The processor generates a sequence of bits encoding a CAN frame and processes the sequence of bits to detect a sequence of PWM periods. The processor stores values of a first parameter of the PWM periods into the first memory, and values of a second parameter of the PWM periods into the second memory. The timer comprises a first register which reads from the first memory a value of the first parameter of a current PWM period. The timer comprises a counter which increases a count number and resets the count number as a function of the value of the first register.

公开(公告)号：US11366778B2

公开(公告)日：2022-06-21

申请号：US16874055

申请日：2020-05-14

Applicant: STMICROELECTRONICS DESIGN AND APPLICATION S.R.O. ,  STMICROELECTRONICS APPLICATION GMBH

Inventor： Fred Rennig ,  Ludek Beran

IPC: G06F13/362 ,  G06F13/40 ,  G06F11/07 ,  H04L12/403 ,  G05B19/042 ,  H03M13/09

Abstract: A device includes a master device, a set of slave devices and a bus. The master device is configured to transmit first messages carrying a set of operation data message portions indicative of operations for implementation by slave devices of the set of slave devices, and second messages addressed to slave devices in the set of slave devices. The second messages convey identifiers identifying respective ones of the slave devices to which the second messages are addressed requesting respective reactions towards the master device within respective expected reaction intervals. The slave devices are configured to receive the first messages transmitted from the master device, read respective operation data message portions in the set of operation data message portions, implement respective operations as a function of the respective operation data message portions read, and receive the second messages transmitted from the master device.

公开(公告)号：US20220109375A1

公开(公告)日：2022-04-07

申请号：US17490793

申请日：2021-09-30

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Design and Application S.R.O.

Inventor： Alberto IORIO ,  Maurizio FORESTA ,  Emilio VOLPI ,  Jan NOVOTNY

IPC: H02M3/335 ,  G01R19/165 ,  H02M3/00 ,  H02M1/00

Abstract: A synchronous rectifier driver circuit is configured to drive a synchronous rectifier FET and includes a first terminal configured to be connected to a source terminal of the synchronous rectifier FET. A second terminal is configured to be connected to a drain terminal of the synchronous rectifier FET, and a third terminal is configured to be connected to a gate terminal of the synchronous rectifier FET. The synchronous rectifier driver circuit is configured to measure the voltage between the second terminal and the first terminal, and detect a switch-on instant in which the measured voltage reaches a first threshold value and a switch-off instant in which the measured voltage reaches a second threshold value. The synchronous rectifier driver circuit generates a drive signal between the third terminal and the first terminal as a function of the measured voltage.