公开(公告)号：US5371765A

公开(公告)日：1994-12-06

申请号：US911847

申请日：1992-07-10

Applicant: John H. Guilford

Inventor： John H. Guilford

IPC: H03B28/00 ,  G06F1/03 ,  H03D3/24

CPC classification number: G06F1/0328

Abstract: A direct digital synthesizer of the phase-accumulator type, constructed entirely of binary-radix digital hardware, generates signals with decimally-defined frequency resolution. The synthesizer is supplied with a clock signal which is also decimally-defined. The usual decimal-binary incompatibility problems of such a combination are overcome by the use of a phase accumulator which is partitioned into two segments. The first segment is assigned the most significant portion of the desired frequency, and the other segment is assigned the remaining portion of the desired frequency. The two segments have different arithmetic moduli. Typically, the modulus of the first segment is a power of two, while that of the second segment is an integer other than a power of two. A procedure is given for determining both the point of partition and the second arithmetic modulus.

Abstract translation: 完全由二进制数字硬件构成的相位累加器类型的直接数字合成器产生具有十进制定义的频率分辨率的信号。 合成器提供了也被十进制定义的时钟信号。 这种组合的通常的十进制 - 二进制不兼容性问题通过使用被分成两个段的相位累加器来克服。 第一段被分配为期望频率的最高有效部分，另一个段被分配为期望频率的剩余部分。 两段具有不同的算术模量。 通常，第一段的模量是2的幂，而第二段的模数是除二的幂之外的整数。 给出了确定分区点和第二算术模数两者的过程。

公开(公告)号：US5361046A

公开(公告)日：1994-11-01

申请号：US995486

申请日：1992-12-22

Applicant: John D. Kaewell, Jr. ,  David M. Cooley

Inventor： John D. Kaewell, Jr. ,  David M. Cooley

IPC: G06F1/03 ,  H04L27/12 ,  H03C3/00 ,  H04L27/00 ,  H04L27/18

CPC classification number: G06F1/0328 ,  H04L27/122

Abstract: A modulator capable of providing a fractional sample or symbol 995486 time employs a decimation counter (23) responsive to a clock having a frequency equal to M/N.times.(data symbol clock), where M is an interpolation factor and N is a decimation factor, for generating a data symbol clock to select FSK symbols from a sampled data array (21). A multiplier (26) receives the FSK symbols and multiplies the symbols by a weighting factor determined by the decimation counter. When the decimation counter wraps around due to a modulo M operation, a fractional weight is calculated for the current FSK symbol, then a new FSK symbol is selected, and then a fractional weight is calculated for the new FSK symbol. When the decimation counter has not wrapped, the full weighting, N, is output for the current FSK symbol.

Abstract translation: 能够提供分数样本或符号995486时间的调制器响应于具有等于M / Nx（数据符号时钟）的频率的时钟来采用抽取计数器（23），其中M是内插因子，N是抽取因子， 用于产生数据符号时钟以从采样数据阵列（21）中选择FSK符号。 乘法器（26）接收FSK符号并将符号乘以由抽取计数器确定的加权因子。 当抽取计数器由于模M运算而包围时，计算当前FSK符号的分数权重，则选择新的FSK符号，然后计算新的FSK符号的分数权重。 当抽取计数器未包装时，输出当前FSK符号的全加权值N。

公开(公告)号：US4956798A

公开(公告)日：1990-09-11

申请号：US389076

申请日：1989-08-03

Applicant: Bryan J. Dinteman

Inventor： Bryan J. Dinteman

IPC: H03B28/00 ,  G06F1/03

CPC classification number: G06F1/0328

Abstract: An arbitrary waveform generator using packet data words to represent segments of a desired complex waveform includes a variable clock. Each packet data word contains a clock control word that is used to control the variable clock frequency so that the duration of each segment is adjusted to produce the desired complex waveform.

公开(公告)号：US3639913A

公开(公告)日：1972-02-01

申请号：US3639913D

申请日：1969-11-10

Applicant: NORTH AMERICAN ROCKWELL

Inventor： WATSON GEORGE A

IPC: G06F1/02 ,  G06F1/03 ,  G10H1/057 ,  G10H1/18 ,  G10H1/20 ,  G10H7/04 ,  G06F15/34

CPC classification number: G10H7/04 ,  G06F1/02 ,  G06F1/0328 ,  G10H1/0575 ,  G10H1/182 ,  G10H1/20

Abstract: A memory contains digital data of related informational content in a plurality of discrete locations identified by respective addresses. The memory is addressed, or accessed, at a rate which depends upon the desired spacing between data from the various locations as it is sequentially read from the memory. In a specific embodiment, the data constitutes amplitude values of a complex waveform of the type produced by a musical instrument, at equally spaced points in time along an axis of the waveform. Apparatus for addressing the memory at any of a plurality of selectively controlled rates includes a calculator for continuously computing a set of numbers each defining a different spacing between the data during readout of the memory. When a desired rate of readout is selected, as by selecting a desired frequency of repetition of a complete cycle of the stored waveform, the number associated with that rate is sampled from the computed set and is periodically increased by its own value to identify appropriate data addresses in the memory, for accessing that data, at intervals of the periodic increase corresponding to the desired rate of readout.

公开(公告)号：US20240281019A1

公开(公告)日：2024-08-22

申请号：US18170100

申请日：2023-02-16

Applicant: Rohde & Schwarz GmbH & Co. KG

Inventor： Florian Galler ,  Julius Seeger

IPC: G06F1/02 ,  G06F1/03 ,  G06F1/08

CPC classification number: G06F1/022 ,  G06F1/0328 ,  G06F1/08

Abstract: The measurement circuit includes a clock input, a frequency converter circuit, and a first signal generator circuit. The clock input is configured to receive a reference clock signal. The first signal generator circuit includes a first clock generator circuit configured to generate a first clock signal having an adaptable frequency based on the reference clock signal. The first signal generator circuit further includes a first direct digital synthesizer (DDS) circuit configured to generate a local oscillator (LO) signal based on the first clock signal and based on an adaptable frequency tuning word (FTW) of the first DDS circuit. The adaptable frequency of the first clock signal and the adaptable FTW of the first DDS circuit are configured such that an IF signal is free of spurs emitted by the first DDS circuit at least in a predetermined frequency band.

公开(公告)号：US12028083B2

公开(公告)日：2024-07-02

申请号：US18060856

申请日：2022-12-01

Applicant: Analog Devices International Unlimited Company

Inventor： Krishnan Unni Unnikrishnapillai

IPC: G06F1/03 ,  H03L7/099 ,  H03M1/12 ,  H03M1/66

CPC classification number: H03L7/0994 ,  G06F1/0328 ,  H03L7/0992 ,  H03M1/12 ,  H03M1/66

Abstract: A numerically controlled oscillator system for maintaining a consistent phase reference while switching data rates may include a numerically controlled oscillator (NCO) circuit. The NCO circuit may include a phase accumulator, a phase-to-signal mapping circuit, and a first free-running counter. The phase accumulator may receive a new phase value as an input in response to an update signal. The phase-to-signal mapping circuit may map a value from the phase accumulator to a periodic signal. The first free-running counter may continue counting, without being reset, while the numerically controlled oscillator system is switching digital data rates. The first free-running counter may be configured to provide the new phase value to the phase accumulator using a representation of a counter value of the first free-running counter and a frequency tuning word defined by a representation of a frequency of the periodic signal.

公开(公告)号：US09864579B2

公开(公告)日：2018-01-09

申请号：US15408747

申请日：2017-01-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sascha Junghans ,  Matthias Klein ,  Thomas Schlipf

IPC: G06F3/00 ,  G06F5/00 ,  G06F7/544 ,  G06F7/57 ,  G06F17/30

CPC classification number: G06F7/544 ,  G06F1/0328 ,  G06F1/1615 ,  G06F7/57 ,  G06F9/3838 ,  G06F12/1018 ,  G06F17/30109 ,  G06F17/30949 ,  G06F2212/401

Abstract: Creating hash values based on bit values of an input vector. An apparatus includes a first and a second hash table, a first and second hash function generator adapted to configure a respective hash function for a creation of a first and second hash value based on the bit values of the input vector. The hash values are stored in the respective hash tables. An evaluation unit includes a comparison unit to compare a respective effectiveness of the first hash function and the second hash function, and an exchanging unit responsive to the comparison unit adapted to replace the first hash function by the second hash function.

公开(公告)号：US09837989B2

公开(公告)日：2017-12-05

申请号：US14729013

申请日：2015-06-02

Applicant: Syntropy Systems, LLC

Inventor： Christopher Pagnanelli

IPC: G06F1/02 ,  G06F1/03 ,  H03H17/04

CPC classification number: H03H17/04 ,  G06F1/022 ,  G06F1/0328

Abstract: Provided are, among other things, systems, apparatuses methods and techniques for generating discrete-time sinusoidal sequences. One such apparatus includes a plurality of parallel processing branches, with each of the parallel processing branches operating at a subsampled rate and utilizing a recursive filter to generate sub-rate samples which represent a different subsampling phase of a complete signal that is output by the apparatus.

公开(公告)号：US20160342174A1

公开(公告)日：2016-11-24

申请号：US15230484

申请日：2016-08-08

Applicant: SHENZHEN HUIDING TECHNOLOGY CO., LTD.

Inventor： Guangyao Wang

IPC: G06F1/03 ,  H03K3/012

CPC classification number: G06F1/0321 ,  G06F1/022 ,  G06F1/03 ,  G06F1/0328 ,  G06F1/035 ,  H03K3/012

Abstract: A sine wave generating apparatus comprises: a phase accumulating module, configured to acquire configuration information of a sine wave, and generate address information comprising integer address information and decimal address information; a value searching module, configured to search for first data information and second data information of the sine wave according to the integer address information; an interpolation module, configured to conduct interpolation between the first data information and the second data information, and acquire interpolation original data information of the sine wave according to the decimal address information; a random truncating module, configured to conduct truncation processing on the interpolation original data according to the bit width of the decimal address information and a pseudorandom sequence output value to acquire final interpolation data information of the sine wave; and a sine wave generating module, configured to generate image information of the sine wave according to the final interpolation data information of the sine wave.

Abstract translation: 正弦波发生装置包括：相位累积模块，被配置为获取正弦波的配置信息，并生成包括整数地址信息和十进制地址信息的地址信息; 值搜索模块，被配置为根据整数地址信息搜索正弦波的第一数据信息和第二数据信息; 插值模块，被配置为在所述第一数据信息和所述第二数据信息之间进行插值，并且根据所述十进制地址信息获取所述正弦波的插值原始数据信息; 一个随机截断模块，被配置为根据十进制地址信息的位宽和伪随机序列输出值对插值原始数据进行截断处理，以获取正弦波的最终内插数据信息; 以及正弦波产生模块，被配置为根据正弦波的最终内插数据信息生成正弦波的图像信息。

公开(公告)号：US09501087B1

公开(公告)日：2016-11-22

申请号：US14742369

申请日：2015-06-17

Applicant: RAYTHEON COMPANY

Inventor： Matthew J. Koeth ,  Michael R. Patrizi

IPC: H03B21/00 ,  G06F1/03

CPC classification number: G06F1/0321 ,  G06F1/022 ,  G06F1/0328

Abstract: A frequency-agile frequency source. The frequency source includes an oscillator having an output and being configured to generate a signal at a first frequency at the output, a first direct digital synthesizer (DDS) having an output and a sampling clock input connected to the output of the oscillator, a filter amplifier block having an input directly connected to the output of the first DDS and an output, and a second DDS having a sampling clock input directly connected to the output of the filter amplifier block. The filter amplifier block is a substantially linear time-invariant element having a frequency response, the magnitude of the frequency response being at least 12 dB lower, at a second frequency within the first Nyquist zone of the first frequency, than at a third frequency above the first Nyquist zone of the first frequency.

Abstract translation: 频率敏捷频率源。 频率源包括具有输出并被配置为在输出处以第一频率产生信号的振荡器，具有连接到振荡器的输出的输出和采样时钟输入的第一直接数字合成器（DDS），滤波器 具有直接连接到第一DDS的输出的输入和输出的放大器块，以及具有直接连接到滤波器放大器块的输出的采样时钟输入的第二DDS。 滤波器放大器块是具有频率响应的基本上线性的时间不变元件，频率响应的幅度在第一频率的第一奈奎斯特区内的第二频率处比在第三频率以上的第三频率处低至少12dB 第一个奈奎斯特区的第一个频率。