公开(公告)号：US20070070009A1

公开(公告)日：2007-03-29

申请号：US11525834

申请日：2006-09-25

Applicant: Ikuko Mori ,  Ryutaro Oke

Inventor： Ikuko Mori ,  Ryutaro Oke

IPC: G09G3/36

CPC classification number: G09G3/3648 ,  G09G3/3614 ,  G09G2310/0229 ,  G09G2310/061 ,  G09G2320/0204 ,  G09G2320/0247 ,  G09G2320/0261

Abstract: An afterimage produced when a hold response display is used in an I/P conversion display mode is reduced. This is achieved by a display device comprising: a plurality of drain electrode lines and a plurality of gate electrode lines arranged in a matrix; and pixel areas, each surrounded by two adjacent drain electrode lines and two adjacent gate electrode lines, each pixel area having a TFT element, the assembly of the pixel areas defining a display area, a drain electrode of the TFT element electrically connected to the drain electrode line, a source electrode of the TFT element electrically connected to a pixel electrode, a signal of positive polarity and a signal of negative polarity alternately applied to the pixel electrode a first frame number of times, wherein there is provided a specific period in which a signal of same polarity is applied in succession to the pixel electrode a second frame number of times that is greater than the first frame number, and in the specific period, a signal of a gray scale level lower than those in the first half and second half of the frames is applied.

Abstract translation: 当在I / P转换显示模式中使用保持响应显示时产生的余像被减少。 这通过显示装置实现，该显示装置包括：排列成矩阵的多个漏电极线和多个栅电极线; 以及像素区域，每个被两个相邻的漏电极线和两个相邻的栅电极线围绕，每个像素区域具有TFT元件，所述像素区域的组合限定显示区域，TFT元件的漏极电连接到漏极 电极线，与像素电极电连接的TFT元件的源电极，正极性的信号和负极性的信号交替施加到像素电极的第一帧次数，其中提供了一个特定的周期，其中 与像素电极连续地施加相对于第一帧数的第二帧次数相同极性的信号，在特定的周期内，灰度级的信号低于前半部和第二帧的信号 一半的帧被应用。

公开(公告)号：US20070046811A1

公开(公告)日：2007-03-01

申请号：US11475878

申请日：2006-06-28

Applicant: Tadayoshi Kimura ,  Himio Yamauchi

Inventor： Tadayoshi Kimura ,  Himio Yamauchi

IPC: H04N11/20 ,  H04N7/01

CPC classification number: H04N7/012 ,  G09G2310/0229 ,  G09G2320/103 ,  H04N5/144 ,  H04N7/0137

Abstract: According to one embodiment, a motion-adaptive non-interlace conversion apparatus includes an interference elimination process circuit which executes a cross-color & dot interference elimination process, an intra-field interpolation process circuit which generates an intra-field interpolation signal using a signal that is obtained by delaying a processed signal, which is subjected to the interference elimination process, with a delay corresponding to 1 field, an inter-field interpolation process circuit which generates an inter-field interpolation signal by using the processed signal and a pre-process signal which is yet to be subjected to the cross-color & dot interference elimination process, a motion detection circuit which obtains a motion detection signal, a mixing circuit which mixes the intra-field interpolation signal and the inter-field interpolation signal with a mixing ratio corresponding to the motion detection signal and outputs a mixed signal, and a multiple-speed conversion circuit which executes a multiple-speed conversion process.

Abstract translation: 根据一个实施例，运动自适应非隔行转换装置包括执行交叉色和点干扰消除处理的干扰消除处理电路，使用信号产生场内插值信号的场内插值处理电路 通过使经过干扰消除处理的处理信号延迟对应于1场的延迟，通过使用处理信号产生场间插值信号的场间插值处理电路获得， 未经过色彩和点干扰消除处理的处理信号，获取运动检测信号的运动检测电路，将场内插值信号与场间插值信号混合的混合电路与 混合比率，并输出混合信号和多速转换 执行多速转换处理的离子电路。

公开(公告)号：US07161602B2

公开(公告)日：2007-01-09

申请号：US10907609

申请日：2005-04-07

Applicant: Pei-Min Shan

Inventor： Pei-Min Shan

IPC: G09K9/32 ,  G09K9/40 ,  G09G5/00 ,  H04N7/01 ,  H03L7/00 ,  H04N5/14

CPC classification number: G09G3/20 ,  G09G2310/0229 ,  H04N5/142 ,  H04N7/012 ,  H04N7/0142

Abstract: A pixel interpolation method includes: utilizing a plurality of pixel pairs on two successive scan lines to determine at least one first possible angle; utilizing a plurality of pixel value distribution trends of the two successive scan lines to determine at least one second possible angle; comparing pixel values of a plurality of pairs of neighboring pixels to detect whether the pixel values are larger than a threshold value in order to determine at least one third possible angle; determine a most appropriate angle according to the first, second, and third possible angles; detecting whether the most appropriate angle is correct by examining that the most appropriate angle is in a group; and utilizing a first pixel on the upper scan line of the two successive scan lines and a second pixel on the bottom scan line of the two successive scan lines to interpolate the a target pixel.

Abstract translation: 像素插值方法包括：利用两个连续扫描线上的多个像素对来确定至少一个第一可能的角度; 利用两个连续扫描线的多个像素值分布趋势来确定至少一个第二可能角度; 比较多个相邻像素对的像素值，以检测像素值是否大于阈值，以便确定至少一个第三可能的角度; 根据第一，第二和第三可能角度确定最合适的角度; 通过检查最适合的角度在一组中来检测最合适的角度是否正确; 并且利用两个连续扫描线的上扫描线上的第一像素和两个连续扫描线的底扫描线上的第二像素来内插目标像素。

公开(公告)号：US07157850B2

公开(公告)日：2007-01-02

申请号：US10931094

申请日：2004-09-01

Applicant: Toshihiko Miyazaki ,  Takeo Ono ,  Hideaki Mitsutake ,  Mitsutoshi Hasegawa ,  Eiji Yamaguchi ,  Shuji Yamada ,  Yasuyuki Todokoro

Inventor： Toshihiko Miyazaki ,  Takeo Ono ,  Hideaki Mitsutake ,  Mitsutoshi Hasegawa ,  Eiji Yamaguchi ,  Shuji Yamada ,  Yasuyuki Todokoro

IPC: H01J1/62

CPC classification number: G09G3/2011 ,  G09G3/2014 ,  G09G3/22 ,  G09G5/02 ,  G09G2310/0229 ,  G09G2310/0267 ,  G09G2310/027 ,  G09G2320/0276 ,  G09G2320/0626 ,  G09G2330/02 ,  G09G2330/027 ,  G09G2330/04 ,  G09G2340/125 ,  H01J1/316 ,  H01J29/02 ,  H01J29/028 ,  H01J29/04 ,  H01J29/085 ,  H01J29/86 ,  H01J29/864 ,  H01J29/90 ,  H01J29/92 ,  H01J29/94 ,  H01J31/127 ,  H01J2201/3165 ,  H01J2201/319 ,  H01J2329/02 ,  H01J2329/0489 ,  H01J2329/323 ,  H01J2329/8625 ,  H01J2329/863 ,  H01J2329/864 ,  H01J2329/8645 ,  H01J2329/8655 ,  H01J2329/866 ,  H01J2329/90 ,  H01J2329/92 ,  H04N5/70 ,  H04N7/012 ,  H04N9/12 ,  H04N9/30

Abstract: An image formation apparatus is disclosed which includes, within an enclosure configured by a pair of substrates placed face to face and an external frame placed between the substrates, an electron source placed on one of the pair of substrates, an image formation material placed on the other substrate, and spacers placed between the substrates, characterized in that the spacers and the external frame is conductive and device is provided for electrically connecting the spacers and the external frame so that the equipotential surfaces between the spacers and the external frame are quasi-parallel when driven.

Abstract translation: 公开了一种图像形成装置，其包括在由面对面放置的一对基板和设置在基板之间的外部框架构成的外壳内，放置在一对基板之一上的电子源，放置在该基板上的图像形成材料 其它基板和位于基板之间的间隔物，其特征在于，所述间隔件和所述外框架是导电的，并且所述装置被设置用于电连接所述间隔件和所述外框架，使得所述间隔件和所述外框架之间的等电位面是准 - 驱动时并联

公开(公告)号：US20060262217A1

公开(公告)日：2006-11-23

申请号：US11357364

申请日：2006-02-17

Applicant: Laurence Thompson ,  Dale Adams

Inventor： Laurence Thompson ,  Dale Adams

IPC: H04N11/20 ,  H04N7/01

CPC classification number: H04N5/21 ,  G09G5/39 ,  G09G5/393 ,  G09G2310/0229 ,  H04N5/14 ,  H04N5/4401 ,  H04N5/66 ,  H04N5/775 ,  H04N5/85 ,  H04N7/0112 ,  H04N7/012 ,  H04N9/8042

Abstract: A digital image processor is provided. The digital image processor includes a deinterlacing processor that is implemented upon a digital processing unit. The deinterlacing processor is coupled to an input operable to receive an interlaced video stream, a digital memory for storing portions of the interlaced video signal, and an output operable to transmit a deinterlaced video stream. The deinterlacing processor is operable to perform frequency analysis upon the received interlaced video stream in order to generate the deinterlaced video stream having reduced motion artifacts.

公开(公告)号：US20060176262A1

公开(公告)日：2006-08-10

申请号：US10541093

申请日：2004-04-08

Applicant: Toshiyuki Fujine ,  Takashi Yoshii

Inventor： Toshiyuki Fujine ,  Takashi Yoshii

IPC: G09G3/36

CPC classification number: G09G3/3611 ,  G09G2310/0229 ,  G09G2320/0247 ,  G09G2320/0252 ,  G09G2320/041 ,  G09G2340/16 ,  G09G2360/18

Abstract: When a video signal type detecting section detects an interlace signal, an I/P conversion section subjects the interlace signal to I/P conversion, and the signal is supplied to an enhancing conversion section. In the enhancing conversion section, the image data is subjected to enhancing conversion, so that optical characteristics of a liquid crystal display panel is corrected. On this occasion, the degradation of the quality of a reproduced image due to the enhancement of unwanted changes (false signal), by causing the degree of the enhancing conversion of the image data having been subjected to the I/P conversion to be lower than the degree of the enhanced conversion of the image data inputted as the progressive signal. As a result, the enhancing conversion of the input image data is performed in such a manner as to correct the optical response characteristics of the liquid crystal panel, so that it is possible to restrain the enhancement of unwanted changes occurring at the outline of the image on the occasion of subjecting the interlace image signal to the I/P conversion, and hence high-quality image reproduction is realized.

公开(公告)号：US20060028583A1

公开(公告)日：2006-02-09

申请号：US10912647

申请日：2004-08-04

Applicant: Walter Lin ,  Jiande Jiang

Inventor： Walter Lin ,  Jiande Jiang

IPC: H04N9/74

CPC classification number: G09G5/14 ,  G09G5/391 ,  G09G5/395 ,  G09G5/397 ,  G09G2310/0229 ,  G09G2340/0407 ,  G09G2340/0435 ,  G09G2340/12 ,  G09G2340/125 ,  G09G2360/18 ,  H04N5/45 ,  H04N7/012 ,  H04N21/4316 ,  H04N21/440218 ,  H04N21/440263 ,  H04N21/440281

Abstract: The present invention provides a system and method for overlaying video from different video sources on a display device. The sources may include a primary video source that provides first image data in the form of a first video signal, and an overlay video source that provides second image data in the form of a second video signal and a fast blank signal. The system encodes the fast blank signal into the second video signal to form encoded image data. The fast blank signal can occupy one bit of the encoded image data. The system stores the first image data and the encoded image data in a frame buffer. A controller reads the first image data and the encoded image data from the frame buffer. The controller processes and decodes encoded image data, extracting the fast blank signal. The controller then uses the extracted fast blank signal to combine the second image data and the first image data, effective to overlay an image from the overly video source onto an image from the primary video source.

Abstract translation: 本发明提供一种用于在显示设备上覆盖来自不同视频源的视频的系统和方法。 源可以包括以第一视频信号的形式提供第一图像数据的主视频源和以第二视频信号和快速空白信号的形式提供第二图像数据的覆盖视频源。 系统将快速空白信号编码成第二视频信号以形成编码图像数据。 快速空白信号可以占据编码图像数据的一位。 系统将第一图像数据和编码图像数据存储在帧缓冲器中。 控制器从帧缓冲器读取第一图像数据和编码图像数据。 控制器处理和解码编码图像数据，提取快速空白信号。 然后，控制器使用所提取的快速空白信号来组合第二图像数据和第一图像数据，有效地将来自过度视频源的图像重叠到来自主要视频源的图像上。

公开(公告)号：US20060013243A1

公开(公告)日：2006-01-19

申请号：US11182101

申请日：2005-07-14

Applicant: James Louie ,  Menq Shyu

Inventor： James Louie ,  Menq Shyu

IPC: H04L12/56 ,  H04N9/64

CPC classification number: H04N7/01 ,  G06T3/4023 ,  G09G5/005 ,  G09G5/008 ,  G09G5/18 ,  G09G2300/0408 ,  G09G2310/0229 ,  G09G2340/0414 ,  G09G2340/0421 ,  G09G2340/0435 ,  G09G2340/0442 ,  H03L7/1976 ,  H04L49/10 ,  H04L49/30 ,  H04L49/3018 ,  H04L49/3027 ,  H04N5/14 ,  H04N5/46 ,  H04N7/012 ,  H04N21/42692 ,  H04N21/440218

Abstract: The video signals carried on a multitude of bus lines are selectively applied to multiple input formatters disposed in the input stage of a video signal processor. The input stage includes a multiplexing stage which receives the buses and selectively supplies one ore more of the buses for delivery to each of the input formatters disposed in the video signal processor. A second multiplexing stage also disposed in the input stage receives the bus lines delivered by the first multiplexing stage both in the original as well as in a changed order. Software controlled register bits coupled to the select terminals of the second multiplexing stage select between the original and the reordered bus lines and deliver the selected bus lines to the input formatters. The software controlled register bits are also applied to the select terminals of the multiplexers disposed in the first multiplexing stage.

Abstract translation: 在多个总线上承载的视频信号被选择性地应用于设置在视频信号处理器的输入级中的多个输入格式化器。 输入级包括多路复用级，其接收总线并选择性地提供一个或多个总线以传送到设置在视频信号处理器中的每个输入格式化器。 还设置在输入级中的第二复用级接收由原始的以及改变的顺序由第一多路复用级递送的总线线。 耦合到第二复用级的选择端的软件控制寄存器位在原始总线和重新排序的总线之间进行选择，并将所选择的总线传送到输入格式化器。 软件控制的寄存器位也被施加到设置在第一多路复用级中的多路复用器的选择端。

公开(公告)号：US20060012712A1

公开(公告)日：2006-01-19

申请号：US11182102

申请日：2005-07-14

Applicant: James Louie ,  Menq Shyu

Inventor： James Louie ,  Menq Shyu

IPC: G09G5/00 ,  H03L7/00

CPC classification number: H04N7/01 ,  G06T3/4023 ,  G09G5/005 ,  G09G5/008 ,  G09G5/18 ,  G09G2300/0408 ,  G09G2310/0229 ,  G09G2340/0414 ,  G09G2340/0421 ,  G09G2340/0435 ,  G09G2340/0442 ,  H03L7/1976 ,  H04L49/10 ,  H04L49/30 ,  H04L49/3018 ,  H04L49/3027 ,  H04N5/14 ,  H04N5/46 ,  H04N7/012 ,  H04N21/42692 ,  H04N21/440218

Abstract: To match the output frame rates to the input frame rates, a display clock signal is generated that has a frequency locked to the frequency of a reference clock signal. To generate the display clock signal, the period of the vertical incoming data clock is measured using the reference clock signal. The number of pixels disposed in the output frames is subsequently divided by the measured period. A fractional-N phase-locked loop circuit is adapted to multiply the result of the division with the frequency of the reference clock signal to generate the display clock signal. The display clock signal is also locked to the reference clock signal.

Abstract translation: 为了将输出帧速率与输入帧速率相匹配，产生具有锁定到参考时钟信号频率的频率的显示时钟信号。 为了产生显示时钟信号，使用参考时钟信号测量垂直输入数据时钟的周期。 随后将排列在输出帧中的像素数除以测量周期。 分数N锁相环电路适于将划分结果与参考时钟信号的频率相乘以产生显示时钟信号。 显示时钟信号也被锁定到参考时钟信号。

公开(公告)号：US06985126B2

公开(公告)日：2006-01-10

申请号：US10205558

申请日：2002-07-25

Applicant: Jurgen Jean Louis Hoppenbrouwers ,  Roel Van Woudenberg

Inventor： Jurgen Jean Louis Hoppenbrouwers ,  Roel Van Woudenberg

IPC: G09G345/60

CPC classification number: H04N7/012 ,  G09G3/2022 ,  G09G3/2803 ,  G09G3/2937 ,  G09G3/2944 ,  G09G2310/0229 ,  G09G2320/0247 ,  G09G2320/0261 ,  G09G2320/0266 ,  H04N5/70 ,  H04N7/0132

Abstract: A method for driving a PDP minimizes motion artifacts, like blur and double edges, by using an up-conversion to preferably 100 Hz as in CRTs with Natural Motion, combined with an LSC sub-field distribution. Sub-field groups from two images are combined to form a field for a display image.

Abstract translation: 用于驱动PDP的方法通过使用与自然运动在CRT中的优化为100Hz的上转换结合LSC子场分布来最小化运动伪影，如模糊和双边缘。 来自两个图像的子场组被组合以形成用于显示图像的场。