ACTIVE CELL BALANCING
    72.
    发明公开

    公开(公告)号:US20240204540A1

    公开(公告)日:2024-06-20

    申请号:US18340399

    申请日:2023-06-23

    CPC classification number: H02J7/0019 H01M10/425 H01M10/441 H01M2010/4271

    Abstract: A system includes a first battery, a second battery, an integrated circuit, a capacitor, and an inductor. The first battery has first and second battery terminals. The second battery has a third and fourth battery terminals. The second battery terminal is coupled to the third battery terminal. The integrated circuit includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor is coupled between the first battery terminal and a capacitor terminal. The second transistor is coupled between the capacitor terminal and the second battery terminal. The third transistor is coupled between the third battery terminal and an inductor terminal. The fourth transistor is coupled between the inductor terminal and the fourth battery terminal. The capacitor and the inductor are coupled in series. The capacitor is coupled to the capacitor terminal and the inductor coupled to the inductor terminal.

    BATTERY PACK CONTROLLER AND CONTROL METHOD
    74.
    发明公开

    公开(公告)号:US20240195286A1

    公开(公告)日:2024-06-13

    申请号:US18062903

    申请日:2022-12-07

    Abstract: Enhanced battery pack controllers and control methods are disclosed. One illustrative battery pack controller includes: a monitor circuit that couples to a battery pack load terminal to detect when a voltage of the battery pack load terminal indicates a load condition; a fault detection circuit that couples to a current path through an array of one or more battery cells to detect when a current indicates a fault condition; a switch control circuit that selectively de-asserts a discharge transistor control pin, asserts the discharge transistor control pin, and ramps a voltage or current of the discharge transistor control pin in an open loop fashion for at least 10 ms; and a status detection circuit that in the absence of a fault condition causes the switch control circuit to perform said ramping responsive to detection of the load condition while the discharge transistor control pin is de-asserted.

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