公开(公告)号：US4718057A

公开(公告)日：1988-01-05

申请号：US771339

申请日：1985-08-30

申请人： P. Venkitakrishnan ,  Gururaj Singh ,  Ronald C. Laugesen

发明人： P. Venkitakrishnan ,  Gururaj Singh ,  Ronald C. Laugesen

IPC分类号： H04Q3/42 ,  G06F15/78 ,  G06F17/10 ,  H04M1/253 ,  H04Q1/457 ,  H04Q11/04 ,  H04J1/10 ,  H04J3/02

CPC分类号： G06F15/7832 ,  H04M1/253 ,  H04Q1/4575 ,  H04Q11/0428 ,  H04Q2213/13034 ,  H04Q2213/13103 ,  H04Q2213/13106 ,  H04Q2213/13107 ,  H04Q2213/1319 ,  H04Q2213/13216 ,  H04Q2213/13292 ,  H04Q2213/1332 ,  H04Q2213/13396 ,  H04Q2213/13405

摘要： An all-digital signal processor (DSP) is disclosed which performs pulse code modulation (PCM) coding and decoding (CODEC) filter operations for both received and transmitted signals, among other functions. A user can access various programmable registers via the microprocessor to specify parameters used in the execution of programs by the DSP. Two 19-bit wide bidirectional data busses are provided for time-division multiplexed communication between various elements, which include a random access memory (RAM), an arithmetic-logic unit (ALU), and an interface to a receive-side analog-to-digital (A/D) converter and a transmit-side digital-to-analog (D/A) converter. A programmed logic array (PLA) executes microcode which controls the processing of signals by the ALU section. A variety of other operations can be performed under control of the PLA such as generation of dual-tone multi-frequency (DTMF) signals commonly used in telecommunications. The architecture of the DSP provides a number of user-accessible registers for the storage of parameters and coefficients used in the generation of the DTMF signals, in the CODEC filtering, and in the compression and expansion of signals. The design of the general-purpose DSP is readily expandible to accomodate additional circuit elements and/or more signals to be processed in parallel.

摘要翻译： 公开了一种全数字信号处理器（DSP），其对于接收和发送的信号以及其他功能执行脉冲编码调制（PCM）编码和解码（CODEC）滤波操作。 用户可以通过微处理器访问各种可编程寄存器，以指定由DSP执行程序所使用的参数。 提供两个19位宽的双向数据总线用于各种元件之间的时分多路复用通信，其中包括随机存取存储器（RAM），算术逻辑单元（ALU）以及与接收端模拟到 数字（A / D）转换器和发射侧数模（D / A）转换器。 编程逻辑阵列（PLA）执行控制ALU部分处理信号的微码。 可以在PLA的控制下进行各种其他操作，例如通信中常用的双音多频（DTMF）信号的产生。 DSP的架构提供了许多用户可访问的寄存器，用于存储在DTMEC信号生成中使用的参数和系数，在CODEC滤波以及信号的压缩和扩展中。 通用DSP的设计很容易扩展，以容纳并行处理的附加电路元件和/或更多信号。

公开(公告)号：US11990937B2

公开(公告)日：2024-05-21

申请号：US17821316

申请日：2022-08-22

申请人： Cable Television Laboratories, Inc.

发明人： Mu Xu ,  Zhensheng Jia ,  Junwen Zhang ,  Haipeng Zhang ,  Luis Alberto Campos

IPC分类号： H04B10/2507 ,  H04B10/40 ,  H04B10/69 ,  H04Q11/00

CPC分类号： H04B10/2572 ,  H04B10/40 ,  H04B10/6971 ,  H04Q11/0067 ,  H04Q2213/1319

摘要： An echo cancellation method includes steps of (a) extracting phase-distortion estimates, (b) reconstructing an echo signal, (c) generating a clean signal, and (d) producing a primary signal. Step (a) includes extracting, from a first phase signal, a plurality of phase-distortion estimates, the first phase signal having been estimated from an echo-corrupted signal received at a first coherent transceiver of a coherent optical network. Step (b) includes reconstructing an echo signal from the plurality of phase-distortion estimates and a transmitted signal transmitted by the first coherent transceiver. Step (c) includes generating a clean signal as a difference between the reconstructed echo signal and the first phase signal. Step (d) includes producing a primary signal by mapping each of a plurality of clean-phase estimates of the clean signal to one of a plurality of constellation symbols associated with a modulation scheme of the primary signal.

公开(公告)号：US09537590B2

公开(公告)日：2017-01-03

申请号：US14132978

申请日：2013-12-18

申请人： GENESIS TECHNICAL SYSTEMS CORP.

发明人： Stephen P. Cooke ,  Tino Zottola

IPC分类号： H04J3/06 ,  H04B7/212 ,  H04W4/00 ,  G06K5/00 ,  H04J14/02 ,  H04B1/06 ,  H04L1/24 ,  H04L12/28 ,  H04L12/42 ,  H04M11/06 ,  H04L7/00

CPC分类号： H04J3/0617 ,  H04J3/0638 ,  H04J3/0688 ,  H04L1/242 ,  H04L7/0008 ,  H04L12/2865 ,  H04L12/42 ,  H04M11/062 ,  H04Q2213/13039 ,  H04Q2213/13098 ,  H04Q2213/13106 ,  H04Q2213/1319 ,  H04Q2213/13298 ,  H04Q2213/1336 ,  H04Q2213/13389

摘要： Apparatus and methods relating to synchronization of communication equipment are disclosed. Synchronization information received from a bonded communication link can be used to synchronize local and/or remote communication equipment, such as femtocell sites coupled to nodes in a ring network. This may involve isolating a frequency reference signal from a DSL (Digital Subscriber Line) communication link which is a constituent link of a bonded communication link, for example. In a ring network, received synchronization information could be used in synchronizing a locally connected installation of communication equipment, and passed for transmission in the ring network for synchronizing other communication equipment. Such dropping and passing of an analog frequency reference signal could be applied in networks having other topologies as well. At least some embodiments of the invention are applicable to optical links. One or more dedicated wavelengths of an optical link could be used to transfer a frequency reference signal, for example. Other functions, such as quality monitoring, quality reporting, and/or predictive traffic forwarding may be provided in some embodiments.

摘要翻译： 公开了与通信设备的同步相关的装置和方法。 从绑定通信链路接收的同步信息可用于同步本地和/或远程通信设备，例如耦合到环形网络中的节点的毫微微小区站点。 这可以包括例如从作为绑定通信链路的组成链路的DSL（数字用户线路）通信链路隔离频率参考信号。 在环网中，接收到的同步信息可以用于同步本地连接的通信设备的设备，并且被传递以在环网中进行传输以同步其他通信设备。 模拟频率参考信号的这种丢弃和传递也可以应用于具有其他拓扑的网络中。 本发明的至少一些实施例可应用于光链路。 例如，光链路的一个或多个专用波长可以用于传送频率参考信号。 在一些实施例中可以提供其他功能，例如质量监测，质量报告和/或预测性流量转发。

公开(公告)号：US09413539B2

公开(公告)日：2016-08-09

申请号：US14248944

申请日：2014-04-09

申请人： Realtek Semiconductor Corp.

发明人： Hung-Chen Chu ,  Yung Tai Chen ,  Shian-Ru Lin

IPC分类号： H04M1/00 ,  H04M9/00 ,  H04L12/00 ,  H04M3/30 ,  H04Q11/00 ,  H04L12/64

CPC分类号： H04L12/00 ,  H04L12/6418 ,  H04M3/304 ,  H04Q11/00 ,  H04Q2213/13039 ,  H04Q2213/1319

摘要： A Pre-distortion mechanism for transmit path non-linearity in xDSL AFE is disclosed in the present invention. The AFE includes a line driver and a pre-distortion signal generator. The line driver receives an input differential signal and generates an output differential signal. The input differential signal includes a first input signal and a second input signal. The output differential signal includes a first output signal and a second output signal. The line driver receives the first input signal to generate the first output signal and receives the second input signal to generate the second output signal. The pre-distortion signal generator is coupled to input ends and output ends of the line driver. The pre-distortion signal generator generates a pre-distortion signal according to a first difference between the first input signal and the first output signal, and a second difference between the second input signal and the second output signal so as to adjust an output state of the analog front-end transmitter having a pre-distortion mechanism.

摘要翻译： 在本发明中公开了xDSL AFE中的发送路径非线性的预失真机制。 AFE包括线路驱动器和预失真信号发生器。 线路驱动器接收输入差分信号并产生输出差分信号。 输入差分信号包括第一输入信号和第二输入信号。 输出差分信号包括第一输出信号和第二输出信号。 线路驱动器接收第一输入信号以产生第一输出信号并接收第二输入信号以产生第二输出信号。 预失真信号发生器耦合到线路驱动器的输入端和输出端。 预失真信号发生器根据第一输入信号和第一输出信号之间的第一差异产生预失真信号，并产生第二输入信号和第二输出信号之间的第二差值，以便调整输出状态 模拟前端发射机具有预失真机制。

公开(公告)号：US08804699B2

公开(公告)日：2014-08-12

申请号：US12736587

申请日：2009-04-28

申请人： Daniel Monsieux ,  Kris Verbeeck ,  Tim Withofs ,  Bart Vercammen ,  Koen Van Oost ,  Dirk Van De Poel

发明人： Daniel Monsieux ,  Kris Verbeeck ,  Tim Withofs ,  Bart Vercammen ,  Koen Van Oost ,  Dirk Van De Poel

IPC分类号： H04L12/66 ,  H04L12/56

CPC分类号： H04Q11/04 ,  H04Q2213/13003 ,  H04Q2213/13034 ,  H04Q2213/1319 ,  H04Q2213/13196 ,  H04Q2213/13299 ,  H04Q2213/13389

摘要： The present invention concerns a gateway device and a method at the gateway, the gateway device comprising an interface to a residential phone wiring comprising more than one plugging means for connecting at least one analogue phone, a broadband interface to a network comprising a central office, the central office being adapted to provide a first voice service type to the at least one analog phone, an FXS module for providing a voice over IP service over the broadband interface to the at least one analogue phone when the first voice service type is disabled, unbundling detection means for detecting the presence of the first voice service type, connecting the FXS module to the residential phone wiring when the first voice service type is disabled, and disconnecting the FXS module from the residential phone wiring when the first voice service type is enabled, and a management agent for informing a gateway management server when changing from the first voice service type to the voice over IP service and vice versa, so that the same phone number can be used when using the first voice service type or the voice over IP service.

摘要翻译： 本发明涉及网关的网关设备和方法，网关设备包括到住宅电话线路的接口，该接口包括用于将至少一个模拟电话，宽带接口连接到包括中心局的网络的多个插接装置， 所述中心局适于向所述至少一个模拟电话提供第一语音服务类型; FXS模块，用于当所述第一语音服务类型被禁用时，通过所述宽带接口向所述至少一个模拟电话提供IP语音服务; 解除捆绑检测装置，用于检测第一语音服务类型的存在，当禁用第一语音服务类型时将FXS模块连接到住宅电话布线，并且当启用第一语音服务类型时将FXS模块与住宅电话布线断开 以及管理代理，用于在从第一语音服务类型改变为语音音频时通知网关管理服务器 r IP服务，反之亦然，因此在使用第一个语音服务类型或IP语音服务时可以使用相同的电话号码。

公开(公告)号：US08743715B1

公开(公告)日：2014-06-03

申请号：US13012752

申请日：2011-01-24

申请人： Richard Alan Eddy ,  Larry Cantwell

发明人： Richard Alan Eddy ,  Larry Cantwell

IPC分类号： H04L12/26 ,  H04J3/14

CPC分类号： H04J3/0685 ,  H04J3/14 ,  H04L7/10 ,  H04L41/0866 ,  H04L43/50 ,  H04L49/101 ,  H04Q2213/1302 ,  H04Q2213/1304 ,  H04Q2213/13166 ,  H04Q2213/1319

摘要： A network switch includes first and second clock-and-data-recovery (CDR) circuits, a cross-bar switch to couple the first and second CDR circuits, and a first test pattern generation circuit electrically coupled with the first CDR circuit. The first test pattern generation circuit is configured to generate a test pattern and transmit the test pattern from the first CDR circuit to the second CDR circuit via the cross-bar switch. The network switch also includes a first test pattern checking circuit, electrically coupled with the second CDR circuit, to verify the test pattern received at the second CDR circuit.

摘要翻译： 网络交换机包括第一和第二时钟和数据恢复（CDR）电路，耦合第一和第二CDR电路的交叉开关以及与第一CDR电路电耦合的第一测试模式产生电路。 第一测试模式生成电路被配置为生成测试模式，并且经由横杆开关将测试模式从第一CDR电路发送到第二CDR电路。 网络交换机还包括与第二CDR电路电耦合的第一测试模式检查电路，以验证在第二CDR电路处接收的测试模式。

公开(公告)号：US08385327B2

公开(公告)日：2013-02-26

申请号：US12364813

申请日：2009-02-03

申请人： Haijun Wu ,  Hui Sheng

发明人： Haijun Wu ,  Hui Sheng

IPC分类号： H04L12/66

CPC分类号： H04L12/66 ,  H04L12/2867 ,  H04L12/4633 ,  H04L65/1023 ,  H04L65/80 ,  H04M11/062 ,  H04Q11/04 ,  H04Q2213/13039 ,  H04Q2213/13106 ,  H04Q2213/1319 ,  H04Q2213/13196 ,  H04Q2213/13204 ,  H04Q2213/13209 ,  H04Q2213/13213 ,  H04Q2213/13292 ,  H04Q2213/13299 ,  H04Q2213/13335 ,  H04Q2213/13348 ,  H04Q2213/13389

摘要： An integrated access system and method and an integrated access module are provided. The system includes a broadband service interface module (310), a narrowband service interface module (320), and a main control switching interface module (10). The main control switching module (10) includes a broadband service switching module (110) providing a broadband uplink interface and a narrowband service processing module (120) providing a narrowband uplink interface and performing narrowband service data process. The broadband service switching module (110) is connected to the broadband service interface module (310) and the narrowband service interface module (320) though broadband buses (21), so as to collect and switch the narrowband service data. The broad band service switching module (110) is connected with network though the broadband uplink interface, and the narrowband service processing module (120) is connected with network though the narrowband uplink interface. Thus, the broadband service and the narrowband service can be accessed simultaneously.

摘要翻译： 提供了一种集成的访问系统和方法以及集成访问模块。 该系统包括宽带业务接口模块（310），窄带业务接口模块（320）和主控交换接口模块（10）。 主控交换模块（10）包括提供宽带上行接口的宽带业务交换模块（110）和提供窄带上行接口并进行窄带业务数据处理的窄带业务处理模块（120）。 宽带业务交换模块（110）通过宽带总线（21）连接到宽带业务接口模块（310）和窄带业务接口模块（320），以收集和切换窄带业务数据。 宽带业务交换模块（110）通过宽带上行接口与网络连接，窄带业务处理模块（120）通过窄带上行接口与网络连接。 因此，可以同时访问宽带业务和窄带业务。

公开(公告)号：US07773744B1

公开(公告)日：2010-08-10

申请号：US10981285

申请日：2004-11-04

申请人： Daniel M. Joffe

发明人： Daniel M. Joffe

IPC分类号： H04M1/00

CPC分类号： H04M1/738 ,  H04M19/001 ,  H04Q2213/1319 ,  H04Q2213/13305 ,  H04Q2213/1332

摘要： A sealing current system for a subscriber line that comprises a power source coupled to a first end of the subscriber line configured to apply a voltage to the subscriber line. The sealing current termination circuit coupled to a second end of the subscriber line configured to limit a current in the subscriber line, the current produced by the applied voltage.

摘要翻译： 一种用于用户线路的密封电流系统，其包括耦合到所述用户线路的第一端的电源，所述第一端被配置为向所述用户线路施加电压。 耦合到用户线路的第二端的密封电流终端电路被配置为限制用户线路中的电流，即由所施加的电压产生的电流。

公开(公告)号：US20100091979A1

公开(公告)日：2010-04-15

申请号：US12588112

申请日：2009-10-05

申请人： Edmond Celina Jozef OP DE BEECK

发明人： Edmond Celina Jozef OP DE BEECK

IPC分类号： H04M1/00

CPC分类号： H04Q11/04 ,  H04M11/062 ,  H04M11/068 ,  H04Q2213/13034 ,  H04Q2213/13039 ,  H04Q2213/1319 ,  H04Q2213/13209 ,  H04Q2213/13216 ,  H04Q2213/13302 ,  H04Q2213/13306 ,  H04Q2213/1332

摘要： A 7th order splitter for replacing the known 9th order splitter of an ISDN/POTS telecommunication system and reducing thereby the space occupied on the board as well as the cost. The 7th order splitter comprising, between line terminals (Line+, Line−) and POTS/ISDN terminals, the cascade connection of a LC filter cell (L21a, L12b, C21) and several elliptical filter cells (L22a, L22b, C22, C24, C25; L23a, L23b, C23, C26, C27). One or more of these filter cells is associated with a damped series resonance circuit comprising a capacitor (C21; C22; C23) series coupled with an RL circuit (R21, L24; R22, L25; R23, L26) between two winding (L21a, L21b; L22a, L22b; L23a, L23b) of a symmetrical coil of the associated filter cell. Each RL circuit is constituted by the parallel coupling of a resistor (R21; R22; R23) and a coil (L24; L25; L26).

摘要翻译： 用于替换ISDN / POTS电信系统的已知的9级分离器的七阶分离器，从而减少板上占用的空间以及成本。 第七级分离器包括在线路终端（Line +，Line-）和POTS / ISDN终端之间，LC滤波器单元（L21a，L12b，C21）和若干椭圆滤波器单元（L22a，L22b，C22，C24， C25; L23a，L23b，C23，C26，C27）。 这些滤波器单元中的一个或多个与阻尼串联谐振电路相关联，该阻尼串联谐振电路包括与两个绕组（L21a，L2）之间的RL电路（R21，L24; R22，L25; R23，L26）耦合的电容器（C21; C22; C23） L21b; L22a，L22b; L23a，L23b）。 每个RL电路由电阻器（R21; R22; R23）和线圈（L24; L25; L26）的并联耦合构成。

公开(公告)号：US20090259822A1

公开(公告)日：2009-10-15

申请号：US12100448

申请日：2008-04-10

申请人： Timothy M. Platt ,  Richard Jean-Luc St-Pierre

发明人： Timothy M. Platt ,  Richard Jean-Luc St-Pierre

IPC分类号： G06F15/76

CPC分类号： H04Q11/00 ,  H04N21/434 ,  H04Q2213/13103 ,  H04Q2213/1319 ,  H04Q2213/13305 ,  H04Q2213/1332 ,  H04Q2213/13322 ,  H04Q2213/13332 ,  H04Q2213/13337

摘要： A method of filtering streaming digital data in real time. The method including: (a) initializing and storing a set of m data elements and an associated set of m pointer data from 1 to m in sequence, m an integer greater than 2; (b) receiving in real time a first or next data element of a digital data stream of sequential data elements; (c) simultaneously with (b), replacing a stored data element associated with the pointer datum m with the received data element, changing the pointer datum of m to 1, and incrementing the value of all other pointer data by 1; (d) simultaneously with (b) sorting in order from a low to high all stored data elements; (e) simultaneously with (b), maintaining the association of pointer datum and data elements; (f) simultaneously with (b), filtering all stored data elements; and (g) repeating (b) through (f) multiple times.

摘要翻译： 实时流式传输数字数据的方法。 该方法包括：（a）将一组m个数据元素和一组m个指针数据从1到m依次初始化和存储，m大于2的整数; （b）实时接收顺序数据元素的数字数据流的第一或下一个数据元素; （c）与（b）同时，用接收到的数据元素替换与指针数据m相关联的存储的数据元素，将m的指针数据改变为1，并将所有其他指针数据的值递增1; （d）同时（b）从低到高所有存储的数据元素的顺序排序; （e）同时（b），保持指针数据和数据元素的关联; （f）同时（b），过滤所有存储的数据元素; 和（g）重复（b）至（f）多次。