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公开(公告)号：US20180310390A1
公开(公告)日：2018-10-25
申请号：US15957578
申请日：2018-04-19
Applicant: STMicroelectronics (Alps) SAS , STMicroelectronics S.r.l. , STMicroelectronics Application GmbH
Inventor： Philippe SIRITO-OLIVIER , Giovanni Luca TORRISI , Manuel GAERTNER , Fritz BURKHARDT
CPC classification number: H05B39/02 , B60Q1/00 , B60Q3/80 , H05B33/0806 , H05B33/0815 , H05B39/047
Abstract: The power supply device comprises a supply transistor commanded by a command signal and providing electric power to a lighting module, and a driving means configured to selectively generate, depending on an instruction signal representative of the structure of said at least one lighting module, a first command signal able to command the supply transistor into an ohmic regime, a second command signal able to command the supply transistor into a pulse width modulation regime involving an alternation of ohmic regimes and blocked regimes, and a third command signal able to command the supply transistor into a saturated regime.
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公开(公告)号：US09919334B2
公开(公告)日：2018-03-20
申请号：US14975540
申请日：2015-12-18
Applicant: STMicroelectronics, Inc. , STMICROELECTRONICS S.R.L. , STMicroelectronics International N.V.
Inventor： Simon Dodd , Joe Scheffelin , Dave Hunt , Matt Giere , Dana Gruenbacher , Faiz Sherman
CPC classification number: B05B17/0607 , B05B17/0638 , B05B17/0684 , B41J2/14016 , B41J2/14024 , B41J2/14056 , B41J2/14072 , B41J2/1433 , B41J2/1601 , B41J2/1632 , B41J2/175 , B41J2/17526 , B41J2/1753 , B41J2002/14338 , B41J2002/14491 , H05K1/0212 , H05K1/111 , H05K1/181 , Y10T29/49119
Abstract: The present disclosure is directed to a microfluidic die that includes a plurality of heaters above a substrate, a plurality of chambers and nozzles above the heaters, a plurality of first contacts coupled to the heaters, and a plurality of second contacts coupled to the heaters. The plurality of second contacts are coupled to each other and coupled to ground. The die includes a plurality of contact pads, a first signal line coupled to the plurality of second contacts and to a first one of the plurality of contact pads, and a plurality of second signal lines, each second signal line being coupled to one of the plurality of first contacts, groups of the second signal lines being coupled together to drive a group of the plurality of heaters with a single signal, each group of the second signal lines being coupled to a remaining one of the plurality of contact pads.
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公开(公告)号：US09833806B2
公开(公告)日：2017-12-05
申请号：US14976434
申请日：2015-12-21
Applicant: STMicroelectronics, Inc. , STMICROELECTRONICS S.R.L. , STMicroelectronics International N.V.
Inventor： Simon Dodd , Joe Scheffelin , Dave Hunt , Matt Giere , Dana Gruenbacher , Faiz Sherman
CPC classification number: B05B17/0607 , B05B17/0638 , B05B17/0684 , B41J2/14016 , B41J2/14024 , B41J2/14056 , B41J2/14072 , B41J2/1433 , B41J2/1601 , B41J2/1632 , B41J2/175 , B41J2/17526 , B41J2/1753 , B41J2002/14338 , B41J2002/14491 , H05K1/0212 , H05K1/111 , H05K1/181 , Y10T29/49119
Abstract: The present disclosure is directed to a microfluidic die that includes a plurality of heaters above a substrate, a plurality of chambers and nozzles above the heaters, a plurality of first contacts coupled to the heaters, and a plurality of second contacts coupled to the heaters. The plurality of second contacts are coupled to each other and coupled to ground. The die includes a plurality of contact pads, a first signal line coupled to the plurality of second contacts and to a first one of the plurality of contact pads, and a plurality of second signal lines, each second signal line being coupled to one of the plurality of first contacts, groups of the second signal lines being coupled together to drive a group of the plurality of heaters with a single signal, each group of the second signal lines being coupled to a remaining one of the plurality of contact pads.
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公开(公告)号：US09620438B2
公开(公告)日：2017-04-11
申请号：US14615673
申请日：2015-02-06
Inventor： Roseanne Duca , Valter Motta , Xueren Zhang , Kim-Yong Goh
IPC: H01L23/02 , H01L23/495
CPC classification number: H01L23/49568 , H01L23/4334 , H01L2224/48091 , H01L2224/48247 , H01L2224/48464 , H01L2924/18301 , H01L2924/00014
Abstract: An electronic device includes an integrated circuit chip mounted to a heat slug. The heat slug has a peripheral region having first thickness along a first direction, the peripheral region surrounding a recess region (having a second, smaller, thickness along the first direction) that defines a chip mounting surface along a second direction perpendicular to the first direction. The recess region defines side borders and a nook extends into the heat slug along the side borders. An insulating body embeds the integrated circuit one chip and heat slug. Material of the insulating body fills the nook.
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公开(公告)号：US08878830B2
公开(公告)日：2014-11-04
申请号：US12884986
申请日：2010-09-17
Applicant: Jeffrey Raynor , Abdelouahid Zakriti , Stephane Vivien , Pascal Mellot
Inventor： Jeffrey Raynor , Abdelouahid Zakriti , Stephane Vivien , Pascal Mellot
Abstract: Ambient light is detected by a photodiode circuit by measuring the time taken for a digital output of the photodiode circuit to change state in response to exposure of a photodiode of the photodiode circuit to that ambient light. A nominal time for state change is calculated based on photodiode circuit characteristics. Furthermore, an effective time for the photodiode circuit digital output to change state is determined in a calibration mode where the photodiode has been disconnected and a reference current is applied to the circuit. An illumination value of the detected ambient light is then calculated as a function of: the measured time, the effective time and the nominal time.
Abstract translation: 通过测量光电二极管电路的数字输出所需的时间以响应于光电二极管电路的光电二极管暴露于该环境光而改变状态，由光电二极管电路检测环境光。 基于光电二极管电路特性计算状态变化的标称时间。 此外，在光电二极管已经断开并且将参考电流施加到电路的校准模式中确定用于光电二极管电路数字输出改变状态的有效时间。 然后根据测量的时间，有效时间和标称时间来计算检测到的环境光的照明值。
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Patent Agency Ranking
公开(公告)号：US08873668B2
公开(公告)日：2014-10-28
申请号：US13651883
申请日：2012-10-15
Applicant: STMicroelectronics SA , STMicroelectronics (R&D) Ltd , STMicroelectronics (Grenoble 2) SAS
Inventor： Andrew Ferris , Ignazio Antonino Urzi , Pascal Teissier
IPC: H04L25/34
CPC classification number: G06F13/423
Abstract: A circuit includes a first n-bit communications block and a second m-bit communications block. A controller is configured to control mode of operation for the first and second communications blocks. In a first mode, the first and second communications blocks function as a single communications block for n+m bit communications. In a second mode, the first and second communications blocks operate as substantially independent communications block for n bit communications and m bit communications.
Abstract translation: 电路包括第一n比特通信块和第二m比特通信块。 控制器被配置为控制第一和第二通信块的操作模式。 在第一模式中，第一和第二通信块用作n + m位通信的单个通信块。 在第二模式中，第一和第二通信块作为用于n位通信和m位通信的基本上独立的通信块来操作。
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公开(公告)号：US08458427B2
公开(公告)日：2013-06-04
申请号：US13022099
申请日：2011-02-07
Applicant: Giuseppe Guarnaccia , Raffaele Guarrasi , Radhia Kacem
Inventor： Giuseppe Guarnaccia , Raffaele Guarrasi , Radhia Kacem
IPC: G06F12/00
CPC classification number: G06F13/4059 , Y02D10/14 , Y02D10/151
Abstract: A synchronization system includes a memory and a control circuit. The control circuit includes a write interface for writing data in said memory with a first clock signal, wherein the write interface is configured for operating with a write pointer in response to a write command, a read interface for reading data from said memory with a second clock signal, wherein the read interface is configured for operating with a read pointer in response to a read command, a synchronization circuit for synchronizing said write pointer and said read pointer with a synchronization latency, and an elaboration circuit for elaborating data in memory with an elaboration latency, wherein the elaboration latency is smaller than the synchronization latency.
Abstract translation: 同步系统包括存储器和控制电路。 所述控制电路包括用于以第一时钟信号在所述存储器中写入数据的写入接口，其中所述写入接口被配置为响应写入命令与写入指针一起操作;读取接口，用于以第二时钟信号从所述存储器读取数据 时钟信号，其中所述读取接口被配置为响应于读取命令而与读取指针一起操作，用于使所述写入指针和所述读取指针与同步等待时间同步的同步电路，以及用于在存储器中用 精细延迟，其中精细延迟小于同步等待时间。
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公开(公告)号：US08305474B2
公开(公告)日：2012-11-06
申请号：US12622373
申请日：2009-11-19
Applicant: Matthew Purcell , Graeme Storm , Derek Tolmie , Mhamed El Hachimi , Laurent Simony , Min Qu
Inventor： Matthew Purcell , Graeme Storm , Derek Tolmie , Mhamed El Hachimi , Laurent Simony , Min Qu
CPC classification number: H04N5/3355 , H04N5/3577
Abstract: An image sensor has a per-column ADC arrangement including first and second capacitors allowing a comparator circuit to perform correlated double sampling. The capacitors are continuously connected to, respectively, the analog pixel signal and a ramp signal without use of a hold operation. The comparator circuit comprises a differential input being connected to the junction of the two capacitors and being biased by a reference signal. The reference signal is preferably sampled and held from a reference voltage. The use of a differential input as first stage of the comparator addresses problems arising from ground voltage bounce when a large pixel array images a scene with low contrast. Connectivity of the differential input stage allows the ramp signal to see a constant capacitive load thus reduce image artifacts referred to as smear.
Abstract translation: 图像传感器具有包括允许比较器电路执行相关双重采样的第一和第二电容器的每列ADC布置。 电容器分别连续地连接到模拟像素信号和斜坡信号，而不使用保持操作。 比较器电路包括差分输入端，连接到两个电容器的结，并被参考信号偏置。 参考信号优选地从参考电压采样和保持。 使用差分输入作为比较器的第一级，当大像素阵列以低对比度的场景成像时，可以解决地电压反弹引起的问题。 差分输入级的连接允许斜坡信号看到恒定的电容性负载，从而减少称为污迹的图像伪影。
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公开(公告)号：US20110213944A1
公开(公告)日：2011-09-01
申请号：US13022099
申请日：2011-02-07
Applicant: Giuseppe Guarnaccia , Raffaele Guarrasi , Radhia Kacem
Inventor： Giuseppe Guarnaccia , Raffaele Guarrasi , Radhia Kacem
IPC: G06F12/00
CPC classification number: G06F13/4059 , Y02D10/14 , Y02D10/151
Abstract: A synchronization system includes a memory and a control circuit. The control circuit includes a write interface for writing data in said memory with a first clock signal, wherein the write interface is configured for operating with a write pointer in response to a write command, a read interface for reading data from said memory with a second clock signal, wherein the read interface is configured for operating with a read pointer in response to a read command, a synchronization circuit for synchronizing said write pointer and said read pointer with a synchronization latency, and an elaboration circuit for elaborating data in memory with an elaboration latency, wherein the elaboration latency is smaller than the synchronization latency.
Abstract translation: 同步系统包括存储器和控制电路。 所述控制电路包括用于以第一时钟信号在所述存储器中写入数据的写入接口，其中所述写入接口被配置为响应写入命令与写入指针一起操作;读取接口，用于以第二时钟信号从所述存储器读取数据 时钟信号，其中所述读取接口被配置为响应于读取命令而与读取指针一起操作，用于使所述写入指针和所述读取指针与同步等待时间同步的同步电路，以及用于在存储器中用 精细延迟，其中精细延迟小于同步等待时间。
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90.发明授权Cap including a housing and optically transparent member to protect a camera module lens 有权盖包括壳体和光学透明构件以保护相机模块透镜公开(公告)号：US07880132B2
公开(公告)日：2011-02-01
申请号：US11872226
申请日：2007-10-15
Applicant: Stuart Brodie , Hazel McInnes , Kum Weng Loo , Mickael Miglietti , Eric Saugier
Inventor： Stuart Brodie , Hazel McInnes , Kum Weng Loo , Mickael Miglietti , Eric Saugier
CPC classification number: G03B11/00 , H04N5/2257
Abstract: A camera module lens cap is provided to protect a camera module in a mobile device where the camera module is exposed. The camera module lens cap includes an optically transparent member for positioning adjacent a camera lens, and a housing for carrying the optically transparent member. The housing includes an overhanging lip for engaging a base of the camera module.
Abstract translation: 提供相机模块透镜盖，以保护相机模块暴露在的移动设备中的相机模块。 相机模块透镜盖包括用于定位在相机镜头附近的光学透明构件和用于承载光学透明构件的壳体。 壳体包括用于接合摄像机模块的基座的突出唇缘。
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